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Message-ID: <DM6PR11MB2779664C590484A1601A93298C5BA@DM6PR11MB2779.namprd11.prod.outlook.com>
Date: Thu, 15 Jun 2023 11:08:38 +0000
From: "Jadav, Raag" <raag.jadav@...el.com>
To: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
"mika.westerberg@...ux.intel.com" <mika.westerberg@...ux.intel.com>
CC: "linus.walleij@...aro.org" <linus.walleij@...aro.org>,
"linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"Sangannavar, Mallikarjunappa"
<mallikarjunappa.sangannavar@...el.com>,
"N, Pandith" <pandith.n@...el.com>
Subject: RE: [PATCH v3 2/3] pinctrl: intel: refine ->irq_set_type() hook
> On Thu, Jun 15, 2023 at 12:55:17PM +0300,
> mika.westerberg@...ux.intel.com wrote:
> > On Thu, Jun 15, 2023 at 09:48:12AM +0000, Jadav, Raag wrote:
> > > > On Tue, Jun 13, 2023 at 02:20:53PM +0530, Raag Jadav wrote:
>
> ...
>
> > > > Looking at this I realized that entire temporary variable
> > > > assignments can be done outside of spin lock. You probably would
> > > > need another one for keeping rxinv value.
> > >
> > > Something like this?
>
> Almost, see below.
>
> > > u32 value, rxevcfg;
> > > u32 rxinv = 0;
>
> No assignment here.
>
> u32 rxinv, rxevcfg;
> u32 value;
>
> > > if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
> > > rxevcfg = PADCFG0_RXEVCFG_EDGE_BOTH;
> > > } else if (type & IRQ_TYPE_EDGE_FALLING) {
> > > rxevcfg = PADCFG0_RXEVCFG_EDGE;
> > > } else if (type & IRQ_TYPE_EDGE_RISING) {
> > > rxevcfg = PADCFG0_RXEVCFG_EDGE;
> > > } else if (type & IRQ_TYPE_LEVEL_MASK) {
> > > rxevcfg = PADCFG0_RXEVCFG_LEVEL;
> > > } else {
> > > rxevcfg = PADCFG0_RXEVCFG_DISABLED;
> > > }
>
> Now, if it's fully included in the diff (even with --patience parameter), then
> you may drop {}.
>
> > > if (type == IRQ_TYPE_EDGE_FALLING || type ==
> IRQ_TYPE_LEVEL_LOW)
> > > rxinv = PADCFG0_RXINV;
>
> else
> rxinv = 0;
>
> > > raw_spin_lock_irqsave(&pctrl->lock, flags);
> > >
> > > intel_gpio_set_gpio_mode(reg);
> > >
> > > value = readl(reg);
> > >
> > > value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
> > > value |= rxinv;
> > > value |= rxevcfg << PADCFG0_RXEVCFG_SHIFT;
>
> And I would rewrite these to the standard patterns:
>
> value = (value & ~PADCFG0_RXINV) | rxinv;
> value = (value & ~PADCFG0_RXEVCFG_MASK) | (rxevcfg <<
> PADCFG0_RXEVCFG_SHIFT);
>
> And looking at this, perhaps do shift also outside the lock:
>
> } else {
> rxevcfg = PADCFG0_RXEVCFG_DISABLED;
> }
> rxevcfg <<= PADCFG0_RXEVCFG_SHIFT;
>
> But, taking into account scope of the _RXEVCFG_*, I would add shift directly
> to the definitions and kill that SHIFT entirely:
>
> #define PADCFG0_RXEVCFG_LEVEL (0 << 25)
> #define PADCFG0_RXEVCFG_EDGE (1 << 25)
> #define PADCFG0_RXEVCFG_DISABLED (2 << 25)
> #define PADCFG0_RXEVCFG_EDGE_BOTH (3 << 25)
>
> ...
>
> value = (value & ~PADCFG0_RXINV) | rxinv;
> value = (value & ~PADCFG0_RXEVCFG_MASK) | rxevcfg;
>
> Try that one and look if it looks better. It might even save bytes after all.
Should I add all of this in original patch or send this as a separate patch
on top this series?
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