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Message-ID: <20230719015750.GR9559@dragon>
Date: Wed, 19 Jul 2023 09:57:50 +0800
From: Shawn Guo <shawnguo@...nel.org>
To: Tim Harvey <tharvey@...eworks.com>
Cc: linux-arm-kernel@...ts.infradead.org,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>,
NXP Linux Team <linux-imx@....com>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/2] arm64: dts: freescale: Add imx8mp-venice-gw71xx-2x
On Tue, Jul 18, 2023 at 02:16:22PM -0700, Tim Harvey wrote:
> On Sun, Jul 16, 2023 at 5:27 PM Shawn Guo <shawnguo@...nel.org> wrote:
> >
> > On Wed, Jun 07, 2023 at 10:07:24AM -0700, Tim Harvey wrote:
> > > The Gateworks imx8mp-venice-gw71xx-2x consists of a SOM + baseboard.
> > >
> > > The GW702x SOM contains the following:
> > > - i.MX8M Plus SoC
> > > - LPDDR4 memory
> > > - eMMC Boot device
> > > - Gateworks System Controller (GSC) with integrated EEPROM, button
> > > controller, and ADC's
> > > - PMIC
> > > - SOM connector providing:
> > > - eQoS GbE MII
> > > - 1x SPI
> > > - 2x I2C
> > > - 4x UART
> > > - 2x USB 3.0
> > > - 1x PCI
> > > - 1x SDIO (4-bit 3.3V)
> > > - 1x SDIO (4-bit 3.3V/1.8V)
> > > - GPIO
> > >
> > > The GW71xx Baseboard contains the following:
> > > - GPS
> > > - RJ45 GbE (eQoS)
> > > - off-board I/O connector with UART, I2C, SPI, GPIO
> > > - EERPOM
> > > - PCIe clock generator
> > > - full-length miniPCIe socket with PCI/USB3 (via mux) and USB2.0
> > > - USB Type-C with USB 2.0 host and peripheral support
> > > - Wide range DC input supply
> > >
> > > Signed-off-by: Tim Harvey <tharvey@...eworks.com>
> > > ---
> > > arch/arm64/boot/dts/freescale/Makefile | 1 +
> > > .../dts/freescale/imx8mp-venice-gw71xx-2x.dts | 19 ++
> > > .../dts/freescale/imx8mp-venice-gw71xx.dtsi | 236 ++++++++++++++++++
> > > 3 files changed, 256 insertions(+)
> > > create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx-2x.dts
> > > create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> > > index 62f22b77b38b..b3bb823d0168 100644
> > > --- a/arch/arm64/boot/dts/freescale/Makefile
> > > +++ b/arch/arm64/boot/dts/freescale/Makefile
> > > @@ -101,6 +101,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb
> > > dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb
> > > dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb
> > > dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl.dtb
> > > +dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw71xx-2x.dtb
> > > dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx.dtb
> > > dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw7905-2x.dtb
> > > dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dahlia.dtb
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx-2x.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx-2x.dts
> > > new file mode 100644
> > > index 000000000000..53120fc9cd7f
> > > --- /dev/null
> > > +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx-2x.dts
> > > @@ -0,0 +1,19 @@
> > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > > +/*
> > > + * Copyright 2023 Gateworks Corporation
> > > + */
> > > +
> > > +/dts-v1/;
> > > +
> > > +#include "imx8mp.dtsi"
> > > +#include "imx8mp-venice-gw702x.dtsi"
> > > +#include "imx8mp-venice-gw71xx.dtsi"
> > > +
> > > +/ {
> > > + model = "Gateworks Venice GW71xx-2x i.MX8MP Development Kit";
> > > + compatible = "gateworks,imx8mp-gw71xx-2x", "fsl,imx8mp";
> > > +
> > > + chosen {
> > > + stdout-path = &uart2;
> > > + };
> > > +};
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi
> > > new file mode 100644
> > > index 000000000000..86999f52d4b2
> > > --- /dev/null
> > > +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi
> > > @@ -0,0 +1,236 @@
> > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > > +/*
> > > + * Copyright 2023 Gateworks Corporation
> > > + */
> > > +
> > > +#include <dt-bindings/gpio/gpio.h>
> > > +#include <dt-bindings/leds/common.h>
> > > +#include <dt-bindings/phy/phy-imx8-pcie.h>
> > > +
> > > +/ {
> > > + led-controller {
> > > + compatible = "gpio-leds";
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_gpio_leds>;
> > > +
> > > + led-0 {
> > > + function = LED_FUNCTION_STATUS;
> > > + color = <LED_COLOR_ID_GREEN>;
> > > + gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>;
> > > + default-state = "on";
> > > + linux,default-trigger = "heartbeat";
> > > + };
> > > +
> > > + led-1 {
> > > + function = LED_FUNCTION_STATUS;
> > > + color = <LED_COLOR_ID_RED>;
> > > + gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;
> > > + default-state = "off";
> > > + };
> > > + };
> > > +
> > > + pcie0_refclk: pcie0-refclk {
> >
> > Can we name the node clock-xxx?
> >
> > > + compatible = "fixed-clock";
> > > + #clock-cells = <0>;
> > > + clock-frequency = <100000000>;
> > > + };
> > > +
> > > + pps {
> > > + compatible = "pps-gpio";
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_pps>;
> > > + gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
> > > + status = "okay";
> > > + };
> > > +};
> > > +
> > > +/* off-board header */
> > > +&ecspi2 {
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_spi2>;
> > > + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
> > > + status = "okay";
> > > +};
> > > +
> > > +&gpio4 {
> > > + gpio-line-names =
> > > + "", "", "", "",
> > > + "", "", "", "",
> > > + "dio1", "", "", "dio0",
> > > + "", "", "pci_usb_sel", "",
> > > + "", "", "", "",
> > > + "", "", "", "",
> > > + "dio3", "", "dio2", "",
> > > + "pci_wdis#", "", "", "";
> > > +};
> > > +
> > > +&i2c2 {
> > > + clock-frequency = <400000>;
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_i2c2>;
> > > + status = "okay";
> > > +
> > > + accelerometer@19 {
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_accel>;
> > > + compatible = "st,lis2de12";
> > > + reg = <0x19>;
> >
> > Can we start the property list from these two?
> >
> > > + st,drdy-int-pin = <1>;
> > > + interrupt-parent = <&gpio4>;
> > > + interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
> > > + interrupt-names = "INT1";
> > > + };
> > > +};
> > > +
> > > +&pcie_phy {
> > > + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
> > > + fsl,clkreq-unsupported;
> > > + clocks = <&pcie0_refclk>;
> > > + clock-names = "ref";
> > > + status = "okay";
> > > +};
> > > +
> > > +&pcie {
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_pcie0>;
> > > + reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
> > > + status = "okay";
> > > +};
> > > +
> > > +/* GPS */
> > > +&uart1 {
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_uart1>;
> > > + status = "okay";
> > > +};
> > > +
> > > +/* off-board header */
> > > +&uart3 {
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_uart3>;
> > > + status = "okay";
> > > +};
> > > +
> > > +/* USB1 Type-C front panel */
> > > +&usb3_0 {
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_usb1>;
> > > + fsl,over-current-active-low;
> > > + status = "okay";
> > > +};
> > > +
> > > +&usb3_phy0 {
> > > + status = "okay";
> > > +};
> > > +
> > > +&usb_dwc3_0 {
> > > + /* dual role is implemented but not a full featured OTG */
> > > + adp-disable;
> > > + hnp-disable;
> > > + srp-disable;
> > > + dr_mode = "otg";
> > > + usb-role-switch;
> > > + role-switch-default-mode = "peripheral";
> > > + status = "okay";
> > > +
> > > + connector {
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_usbcon1>;
> > > + compatible = "gpio-usb-b-connector", "usb-b-connector";
> >
> > Start the properties from 'compatible'?
> >
> > Shawn
> >
>
> Hi Shawn,
>
> My notes say that pinctrl should come first (if needed) followed by
> compatible, reg, other props, and finally status (if needed). Assuming
> I'm wrong about that where in the list should pinctrl be and is this
> documented anywhere for future reference?
It's more a recommended idiom than documented/hard rule.
- compatible
- reg
- general properties
- vendor specific properties
- status
Shawn
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