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Message-Id: <20230913064306.1862804-1-mwkim@gaonchips.com>
Date:   Wed, 13 Sep 2023 15:43:07 +0900
From:   Myunguk Kim <mwkim@...nchips.com>
To:     krzysztof.kozlowski@...aro.org
Cc:     alsa-devel@...a-project.org, broonie@...nel.org,
        conor+dt@...nel.org, devicetree@...r.kernel.org, fido_max@...ox.ru,
        joabreu@...opsys.com, krzysztof.kozlowski+dt@...aro.org,
        kuninori.morimoto.gx@...esas.com, lgirdwood@...il.com,
        linux-kernel@...r.kernel.org, mwkim@...nchips.com, perex@...ex.cz,
        robh+dt@...nel.org, tiwai@...e.com, u.kleine-koenig@...gutronix.de,
        xingyu.wu@...rfivetech.com
Subject: Re: [PATCH] ASoC: dwc: Add Single DMA mode support

>> This is not dependent on a specific vendor, 
>> but is intended to describe 
>> the properties of the signal(single/burst request) connection 
>> relationship between i2s and dma.
>
> How does this relationship depend on hardware?

When designing a SoC, it depends on the RTL and Bus connection.
My company has two types of configuration SoC: single and burst 
to meet ASIC customer's requirements.

Thanks,
myunguk

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