[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CAMuHMdXo14JwdJE+b1zdnJ7Re5cn8ugzxueD1a=-n=PUQz7VKw@mail.gmail.com>
Date: Thu, 14 Sep 2023 14:13:19 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Claudiu <claudiu.beznea@...on.dev>
Cc: mturquette@...libre.com, sboyd@...nel.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
ulf.hansson@...aro.org, linus.walleij@...aro.org,
gregkh@...uxfoundation.org, jirislaby@...nel.org,
magnus.damm@...il.com, catalin.marinas@....com, will@...nel.org,
prabhakar.mahadev-lad.rj@...renesas.com,
biju.das.jz@...renesas.com, quic_bjorande@...cinc.com,
arnd@...db.de, konrad.dybcio@...aro.org, neil.armstrong@...aro.org,
nfraprado@...labora.com, rafal@...ecki.pl,
wsa+renesas@...g-engineering.com,
linux-renesas-soc@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-mmc@...r.kernel.org, linux-gpio@...r.kernel.org,
linux-serial@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
Subject: Re: [PATCH 07/37] clk: renesas: rzg2l: lock around writes to mux register
Hi Claudiu,
On Tue, Sep 12, 2023 at 6:52 AM Claudiu <claudiu.beznea@...on.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
>
> SD MUX output (SD0) is further divided by 4 in G2{L, UL}. The divided
> clock is SD0_DIV4. SD0_DIV4 is registered with CLK_SET_RATE_PARENT which
> means a rate request for it is propagated to the MUX and could reach
> rzg2l_cpg_sd_clk_mux_set_parent() concurrently with the users of SD0.
> Add proper locking to avoid concurrent access on SD MUX set rate
> registers.
>
> Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support")
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
Thanks for your patch!
> --- a/drivers/clk/renesas/rzg2l-cpg.c
> +++ b/drivers/clk/renesas/rzg2l-cpg.c
> @@ -189,6 +189,7 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index)
> u32 shift = GET_SHIFT(hwdata->conf);
> const u32 clk_src_266 = 2;
> u32 msk, val, bitmask;
> + unsigned long flags;
> int ret;
>
> /*
> @@ -203,25 +204,27 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index)
> * the index to value mapping is done by adding 1 to the index.
> */
> bitmask = (GENMASK(GET_WIDTH(hwdata->conf) - 1, 0) << shift) << 16;
> + spin_lock_irqsave(&priv->rmw_lock, flags);
> if (index != clk_src_266) {
> writel(bitmask | ((clk_src_266 + 1) << shift), priv->base + off);
>
> msk = off ? CPG_CLKSTATUS_SELSDHI1_STS : CPG_CLKSTATUS_SELSDHI0_STS;
>
> - ret = readl_poll_timeout(priv->base + CPG_CLKSTATUS, val,
> - !(val & msk), 100,
> - CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US);
> - if (ret) {
> - dev_err(priv->dev, "failed to switch clk source\n");
> - return ret;
> - }
> + ret = readl_poll_timeout_atomic(priv->base + CPG_CLKSTATUS, val,
> + !(val & msk), 100,
According to the read_poll_timeout_atomic() documentation,
delay_us should be less than ~10us.
> + CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US);
CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US = 20 ms, which is a long timeout
for an atomic poll.
> + if (ret)
> + goto unlock;
> }
>
> writel(bitmask | ((index + 1) << shift), priv->base + off);
>
> - ret = readl_poll_timeout(priv->base + CPG_CLKSTATUS, val,
> - !(val & msk), 100,
> - CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US);
> + ret = readl_poll_timeout_atomic(priv->base + CPG_CLKSTATUS, val,
> + !(val & msk), 100,
> + CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US);
Likewise.
> +unlock:
> + spin_unlock_irqrestore(&priv->rmw_lock, flags);
> +
> if (ret)
> dev_err(priv->dev, "failed to switch clk source\n");
The rest LGTM.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Powered by blists - more mailing lists