linux-kernel - RE: [PATCH v7 0/3] can: xilinx

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Date: Tue, 19 Dec 2023 06:34:11 +0000
From: "Goud, Srinivas" <srinivas.goud@....com>
To: "Goud, Srinivas" <srinivas.goud@....com>, "wg@...ndegger.com"
	<wg@...ndegger.com>, "mkl@...gutronix.de" <mkl@...gutronix.de>,
	"davem@...emloft.net" <davem@...emloft.net>, "edumazet@...gle.com"
	<edumazet@...gle.com>, "kuba@...nel.org" <kuba@...nel.org>,
	"pabeni@...hat.com" <pabeni@...hat.com>, "robh+dt@...nel.org"
	<robh+dt@...nel.org>, "krzysztof.kozlowski+dt@...aro.org"
	<krzysztof.kozlowski+dt@...aro.org>, "conor+dt@...nel.org"
	<conor+dt@...nel.org>, "p.zabel@...gutronix.de" <p.zabel@...gutronix.de>
CC: "git (AMD-Xilinx)" <git@....com>, "michal.simek@...inx.com"
	<michal.simek@...inx.com>, "linux-can@...r.kernel.org"
	<linux-can@...r.kernel.org>, "netdev@...r.kernel.org"
	<netdev@...r.kernel.org>, "devicetree@...r.kernel.org"
	<devicetree@...r.kernel.org>, "linux-arm-kernel@...ts.infradead.org"
	<linux-arm-kernel@...ts.infradead.org>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>, "appana.durga.rao@...inx.com"
	<appana.durga.rao@...inx.com>
Subject: RE: [PATCH v7 0/3] can: xilinx_can: Add ECC feature support

Ping!

>-----Original Message-----
>From: Srinivas Goud <srinivas.goud@....com>
>Sent: Monday, November 27, 2023 3:58 PM
>To: wg@...ndegger.com; mkl@...gutronix.de; davem@...emloft.net;
>edumazet@...gle.com; kuba@...nel.org; pabeni@...hat.com;
>robh+dt@...nel.org; krzysztof.kozlowski+dt@...aro.org; conor+dt@...nel.org;
>p.zabel@...gutronix.de
>Cc: git (AMD-Xilinx) <git@....com>; michal.simek@...inx.com; linux-
>can@...r.kernel.org; netdev@...r.kernel.org; devicetree@...r.kernel.org;
>linux-arm-kernel@...ts.infradead.org; linux-kernel@...r.kernel.org;
>appana.durga.rao@...inx.com; Goud, Srinivas <srinivas.goud@....com>
>Subject: [PATCH v7 0/3] can: xilinx_can: Add ECC feature support
>
>Add ECC feature support to Tx and Rx FIFOs for Xilinx CAN Controller.
>ECC is an IP configuration option where counter registers are added in IP for
>1bit/2bit ECC errors count and reset.
>Also driver reports 1bit/2bit ECC errors for FIFOs based on ECC error interrupts.
>
>Add xlnx,has-ecc optional property for Xilinx AXI CAN controller to support ECC
>if the ECC block is enabled in the HW.
>
>Add ethtool stats interface for getting all the ECC errors information.
>
>There is no public documentation for it available.
>
>---
>BRANCH: linux-can-next/master
>
>Changes in v7:
>Update with spinlock only for stats counters
>
>Changes in v6:
>Update commit description
>
>Changes in v5:
>Fix review comments
>Change the sequence of updates the stats Add get_strings and get_sset_count
>stats interface Use u64 stats helper function
>
>Changes in v4:
>Fix DT binding check warning
>Update xlnx,has-ecc property description
>
>Changes in v3:
>Update mailing list
>Update commit description
>
>Changes in v2:
>Address review comments
>Add ethtool stats interface
>Update commit description
>
>
>Srinivas Goud (3):
>  dt-bindings: can: xilinx_can: Add 'xlnx,has-ecc' optional property
>  can: xilinx_can: Add ECC support
>  can: xilinx_can: Add ethtool stats interface for ECC errors
>
> .../devicetree/bindings/net/can/xilinx,can.yaml    |   5 +
> drivers/net/can/xilinx_can.c                       | 159 ++++++++++++++++++++-
> 2 files changed, 160 insertions(+), 4 deletions(-)
>
>--
>2.1.1