linux-kernel - RE: [RFC 16/16] riscv: dts: starfive: jh8100: Add clocks and resets nodes

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Date: Wed, 27 Dec 2023 11:02:05 +0000
From: JeeHeng Sia <jeeheng.sia@...rfivetech.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>, "kernel@...il.dk"
	<kernel@...il.dk>, "conor@...nel.org" <conor@...nel.org>,
	"robh+dt@...nel.org" <robh+dt@...nel.org>,
	"krzysztof.kozlowski+dt@...aro.org" <krzysztof.kozlowski+dt@...aro.org>,
	"paul.walmsley@...ive.com" <paul.walmsley@...ive.com>, "palmer@...belt.com"
	<palmer@...belt.com>, "aou@...s.berkeley.edu" <aou@...s.berkeley.edu>,
	"mturquette@...libre.com" <mturquette@...libre.com>, "sboyd@...nel.org"
	<sboyd@...nel.org>, "p.zabel@...gutronix.de" <p.zabel@...gutronix.de>,
	"emil.renner.berthing@...onical.com" <emil.renner.berthing@...onical.com>,
	Hal Feng <hal.feng@...rfivetech.com>, Xingyu Wu <xingyu.wu@...rfivetech.com>
CC: "linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>, Leyfoon Tan
	<leyfoon.tan@...rfivetech.com>
Subject: RE: [RFC 16/16] riscv: dts: starfive: jh8100: Add clocks and resets
 nodes



> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> Sent: Tuesday, December 26, 2023 9:39 PM
> To: JeeHeng Sia <jeeheng.sia@...rfivetech.com>; kernel@...il.dk; conor@...nel.org; robh+dt@...nel.org;
> krzysztof.kozlowski+dt@...aro.org; paul.walmsley@...ive.com; palmer@...belt.com; aou@...s.berkeley.edu;
> mturquette@...libre.com; sboyd@...nel.org; p.zabel@...gutronix.de; emil.renner.berthing@...onical.com; Hal Feng
> <hal.feng@...rfivetech.com>; Xingyu Wu <xingyu.wu@...rfivetech.com>
> Cc: linux-riscv@...ts.infradead.org; devicetree@...r.kernel.org; linux-kernel@...r.kernel.org; linux-clk@...r.kernel.org; Leyfoon Tan
> <leyfoon.tan@...rfivetech.com>
> Subject: Re: [RFC 16/16] riscv: dts: starfive: jh8100: Add clocks and resets nodes
> 
> On 26/12/2023 06:38, Sia Jee Heng wrote:
> > Add SYSCRG/SYSCRG-NE/SYSCRG-NW/SYSCRG-SW/AONCRG clock and reset
> > nodes for JH8100 RISC-V SoC.
> >
> > Signed-off-by: Sia Jee Heng <jeeheng.sia@...rfivetech.com>
> > Reviewed-by: Ley Foon Tan <leyfoon.tan@...rfivetech.com>
> > ---
> 
> ...
> 
> >  		compatible = "simple-bus";
> >  		interrupt-parent = <&plic>;
> > @@ -357,6 +563,99 @@ uart4: serial@...a0000  {
> >  			status = "disabled";
> >  		};
> >
> > +		necrg: necrg@...20000 {
> 
> This is a friendly reminder during the review process.
Thank you for the friendly reminder and your valuable feedback.
I appreciate your guidance during the review process.
Your input is crucial, and I'm committed to delivering high-quality code.
Thanks again for your time and feedback. 
> 
> It seems my or other reviewer's previous comments were not fully
> addressed. Maybe the feedback got lost between the quotes, maybe you
> just forgot to apply it. Please go back to the previous discussion and
> either implement all requested changes or keep discussing them.
I didn't ignore your comment. Instead, I misinterpreted it as suggesting
the use of a dash instead of an underscore for the node's name. I will make
the necessary adjustment and change it back to 'clock-controller'.
> 
> Thank you.
> 
> Best regards,
> Krzysztof