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Message-ID: <869df984-d3e8-4b2d-8724-6829e9c23269@ixit.cz>
Date: Fri, 29 Dec 2023 18:59:11 +0100
From: David Heidelberg <david@...t.cz>
To: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
Cc: krzysztof.kozlowski@...aro.org, agross@...nel.org, andersson@...nel.org,
bhelgaas@...gle.com, conor+dt@...nel.org, conor.dooley@...rochip.com,
devicetree@...r.kernel.org, konrad.dybcio@...aro.org,
krzysztof.kozlowski+dt@...aro.org, kw@...ux.com,
linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-pci@...r.kernel.org, lpieralisi@...nel.org, mani@...nel.org,
robh@...nel.org
Subject: Re: [PATCH v2 1/2] dt-bindings: PCI: qcom: adjust iommu-map for
different SoC
On 29/12/2023 18:17, Manivannan Sadhasivam wrote:
> On Fri, Dec 29, 2023 at 04:36:31PM +0100, David wrote:
>>> + minItems: 1
>> Hello Krzysztof,
>>
>> the driver will accept 0 just fine, so I think this definition may be wrong.
>>
> It's not entirely wrong but the actual SID mapping differs between SoCs.
Sure, I think I can live with this.
>
>> I sent just generic "dt-bindings: PCI: qcom: delimit number of iommu-map entries" which doesn't care about the numbers (in similar fashion as other bindings having iommu-map).
>>
> No, we should not just ignore the MAX limit. If you add <N> number of entries
> exceeding the max SID assigned to PCIe bus, it will fail.
>
> - Mani
Make sense, thanks for explanation.
Reviewed-by: David Heidelberg <david@...t.cz>
>> Tell me what you think.
>>
>> David
>>
--
David Heidelberg
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