linux-kernel - Re: [PATCH v2 25/28] asm-generic/io.h: add iowrite{8,16}

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date: Thu, 25 Jan 2024 22:23:53 +0100
From: "Arnd Bergmann" <arnd@...db.de>
To: "Tudor Ambarus" <tudor.ambarus@...aro.org>,
 "Mark Brown" <broonie@...nel.org>, "Andi Shyti" <andi.shyti@...nel.org>
Cc: "Rob Herring" <robh+dt@...nel.org>, krzysztof.kozlowski+dt@...aro.org,
 "Conor Dooley" <conor+dt@...nel.org>,
 "Alim Akhtar" <alim.akhtar@...sung.com>, linux-spi@...r.kernel.org,
 linux-samsung-soc@...r.kernel.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
 Linux-Arch <linux-arch@...r.kernel.org>,
 André Draszik <andre.draszik@...aro.org>,
 "Peter Griffin" <peter.griffin@...aro.org>,
 "Sam Protsenko" <semen.protsenko@...aro.org>, kernel-team@...roid.com,
 "William McVicker" <willmcvicker@...gle.com>
Subject: Re: [PATCH v2 25/28] asm-generic/io.h: add iowrite{8,16}_32 accessors

On Thu, Jan 25, 2024, at 15:50, Tudor Ambarus wrote:
> This will allow devices that require 32 bits register accesses to write
> data in chunks of 8 or 16 bits.
>
> One SoC that requires 32 bit register accesses is the google gs101. A
> typical use case is SPI, where the clients can request transfers in words
> of 8 bits.
>
> Signed-off-by: Tudor Ambarus <tudor.ambarus@...aro.org>

My feeling is that this operation is rare enough that I'd prefer
it to be open-coded in the driver than made generic here. Making
it work for all corner cases is possible but probably not worth
it.

> +#ifndef writesb_l
> +#define writesb_l writesb_l
> +static inline void writesb_l(volatile void __iomem *addr, const void 
> *buffer,
> +			     unsigned int count)
> +{
> +	if (count) {
> +		const u8 *buf = buffer;
> +
> +		do {
> +			__raw_writel(*buf++, addr);
> +		} while (--count);
> +	}
> +}
> +#endif

There are architectures where writesb() requires an extra
barrier before and/or after the loop. I think there are
others that get the endianess wrong in the generic version
you have here.

> +#ifndef iowrite8_32_rep
> +#define iowrite8_32_rep iowrite8_32_rep
> +static inline void iowrite8_32_rep(volatile void __iomem *addr,
> +				   const void *buffer,
> +				   unsigned int count)
> +{
> +	writesb_l(addr, buffer, count);
> +}
> +#endif

This one is wrong for architectures that have a custom inl()
helper and need to multiplex between inl() and writel() in
iowrite32(), notably x86.

For completeness you would need to add the out-of-line version
in lib/iomap.c for those, plus the corresponding insb_32()
and possibly the respective big-endian versions of those.

If you keep the helper in a driver that is only used on
regular architectures like arm64, it will work reliably.

      Arnd