linux-kernel - Re: [PATCH v2 10/28] spi: s3c64xx: use full mask for {RX, TX}_FIFO

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Message-ID: <e2c25c1b-7fe9-4174-95ed-e867eff14e37@sirena.org.uk>
Date: Thu, 25 Jan 2024 21:48:48 +0000
From: Mark Brown <broonie@...nel.org>
To: Sam Protsenko <semen.protsenko@...aro.org>
Cc: Tudor Ambarus <tudor.ambarus@...aro.org>, andi.shyti@...nel.org,
	arnd@...db.de, robh+dt@...nel.org,
	krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
	alim.akhtar@...sung.com, linux-spi@...r.kernel.org,
	linux-samsung-soc@...r.kernel.org, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
	linux-arch@...r.kernel.org, andre.draszik@...aro.org,
	peter.griffin@...aro.org, kernel-team@...roid.com,
	willmcvicker@...gle.com
Subject: Re: [PATCH v2 10/28] spi: s3c64xx: use full mask for {RX,
 TX}_FIFO_LVL

On Thu, Jan 25, 2024 at 02:03:15PM -0600, Sam Protsenko wrote:
> On Thu, Jan 25, 2024 at 8:50 AM Tudor Ambarus <tudor.ambarus@...aro.org> wrote:

> > +#define S3C64XX_SPI_ST_RX_FIFO_LVL             GENMASK(23, 15)

> What about s3c* architectures, where RX_LVL starts with bit #13, as
> can be seen from .rx_lvl_offset values in corresponding port_configs?
> Wouldn't this change break those?

I should point out that I have a s3c6410 board I care about.

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