linux-kernel - RE: [PATCH v3] dt-bindings: misc: xlnx,sd-fec: convert bindings to yaml

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Message-ID:
 <BY5PR12MB424156FCFE0E76DBCCE80862E27D2@BY5PR12MB4241.namprd12.prod.outlook.com>
Date: Tue, 30 Jan 2024 15:00:50 +0000
From: "Cvetic, Dragan" <dragan.cvetic@....com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>, Rob Herring
	<robh+dt@...nel.org>, Krzysztof Kozlowski
	<krzysztof.kozlowski+dt@...aro.org>, Conor Dooley <conor+dt@...nel.org>,
	"Kiernan, Derek" <derek.kiernan@....com>, Jonathan Corbet <corbet@....net>,
	"Simek, Michal" <michal.simek@....com>, "Erim, Salih" <Salih.Erim@....com>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
	<devicetree@...r.kernel.org>, open list <linux-kernel@...r.kernel.org>, "open
 list:DOCUMENTATION" <linux-doc@...r.kernel.org>, "moderated list:ARM/ZYNQ
 ARCHITECTURE" <linux-arm-kernel@...ts.infradead.org>
Subject: RE: [PATCH v3] dt-bindings: misc: xlnx,sd-fec: convert bindings to
 yaml

Hi Krzysztof,

> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> Sent: Tuesday, January 30, 2024 2:31 PM
> To: Cvetic, Dragan <dragan.cvetic@....com>; Rob Herring
> <robh+dt@...nel.org>; Krzysztof Kozlowski
> <krzysztof.kozlowski+dt@...aro.org>; Conor Dooley <conor+dt@...nel.org>;
> Kiernan, Derek <derek.kiernan@....com>; Jonathan Corbet
> <corbet@....net>; Simek, Michal <michal.simek@....com>; Erim, Salih
> <Salih.Erim@....com>; open list:OPEN FIRMWARE AND FLATTENED DEVICE
> TREE BINDINGS <devicetree@...r.kernel.org>; open list <linux-
> kernel@...r.kernel.org>; open list:DOCUMENTATION <linux-
> doc@...r.kernel.org>; moderated list:ARM/ZYNQ ARCHITECTURE <linux-arm-
> kernel@...ts.infradead.org>
> Subject: Re: [PATCH v3] dt-bindings: misc: xlnx,sd-fec: convert bindings to
> yaml
> 
> On 30/01/2024 13:53, Dragan Cvetic wrote:
> > Convert AMD (Xilinx) sd-fec bindings to yaml format, so it can validate
> > dt-entries as well as any future additions to yaml.
> > Change in clocks is due to IP is itself configurable and
> > only the first two clocks are in all combinations. The last
> > 6 clocks can be present in some of them. It means order is
> > not really fixed and any combination is possible.
> > Interrupt may or may not be present.
> > The documentation for sd-fec bindings is now YAML, so update the
> > MAINTAINERS file.
> > Update the link to the new yaml file in xilinx_sdfec.rst.
> >
> > Signed-off-by: Dragan Cvetic <dragan.cvetic@....com>
> > ---
> > Changes in v2:
> > ---
> > Drop clocks description.
> > Use "contains:" with enum for optional clock-names and update
> > comment explaining diference from the original DT binding file.
> > Remove trailing full stops.
> > Add more details in sdfec-code description.
> > Set sdfec-code to "string" not "string-array"
> > ---
> > Changes in v3:
> > Fix a mistake in example, set interrupt type to 0.
> 
> Why? That's not a correct interrupt type in most of the cases.

The interrupt type is set to active high in IP, cannot be changed with driver.
I keep 0 to be aligned with the original document.
What do you suggest?

> 
> Was this patch tested?
> 
Yes it was, both "make dt_binding_check" and "make dtbs_check"
v2 was my, human mistake. I sent wrong patch. I'm sorry for that.

> ...
> 
> > diff --git a/Documentation/devicetree/bindings/misc/xlnx,sd-fec.yaml
> b/Documentation/devicetree/bindings/misc/xlnx,sd-fec.yaml
> > new file mode 100644
> > index 000000000000..ed87c48a9ee9
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/misc/xlnx,sd-fec.yaml
> > @@ -0,0 +1,136 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/misc/xlnx,sd-fec.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Xilinx SDFEC(16nm) IP
> > +
> > +maintainers:
> > +  - Cvetic, Dragan <dragan.cvetic@....com>
> > +  - Erim, Salih <salih.erim@....com>
> > +
> > +description: |
> 
> Do not need '|' unless you need to preserve formatting.

Accepted, will remove it.

> 
> > +  The Soft Decision Forward Error Correction (SDFEC) Engine is a Hard IP
> block
> > +  which provides high-throughput LDPC and Turbo Code implementations.
> > +  The LDPC decode & encode functionality is capable of covering a range of
> > +  customer specified Quasi-cyclic (QC) codes. The Turbo decode
> functionality
> > +  principally covers codes used by LTE. The FEC Engine offers significant
> > +  power and area savings versus implementations done in the FPGA fabric.
> > +
> 
> 
> > +  xlnx,sdfec-dout-words:
> > +    description: |
> > +      A value 0 indicates that the DOUT_WORDS interface is
> > +      driven with a fixed value and is not present on the device, a value of 1
> > +      configures the DOUT_WORDS to be block based, while a value of 2
> configures the
> > +      DOUT_WORDS input to be supplied for each AXI transaction.
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    enum: [ 0, 1, 2 ]
> > +
> > +
> 
> Just one blank line.

Accepted, will remove it.

Kind Regards
Dragan