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Message-ID: <871q8fplsb.ffs@tglx>
Date: Tue, 12 Mar 2024 15:28:04 +0100
From: Thomas Gleixner <tglx@...utronix.de>
To: Palmer Dabbelt <palmer@...belt.com>
Cc: peterlin@...estech.com, acme@...nel.org, adrian.hunter@...el.com,
 ajones@...tanamicro.com, alexander.shishkin@...ux.intel.com,
 andre.przywara@....com, anup@...infault.org, aou@...s.berkeley.edu,
 atishp@...shpatra.org, conor+dt@...nel.org, Conor Dooley
 <conor.dooley@...rochip.com>, Conor Dooley <conor@...nel.org>,
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 geert+renesas@...der.be, guoren@...nel.org, Heiko Stuebner
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 jolsa@...nel.org, jszhang@...nel.org, krzysztof.kozlowski+dt@...aro.org,
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 linux-riscv@...ts.infradead.org, linux-sunxi@...ts.linux.dev,
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 wens@...e.org, Will Deacon <will@...nel.org>, inochiama@...look.com,
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Subject: Re: [PATCH v9 03/10] irqchip/riscv-intc: Introduce Andes hart-level
 interrupt controller

On Tue, Mar 12 2024 at 07:23, Palmer Dabbelt wrote:
> On Fri, 23 Feb 2024 01:06:44 PST (-0800), tglx@...utronix.de wrote:
>> Contains:
>>
>>   f4cc33e78ba8 ("irqchip/riscv-intc: Introduce Andes hart-level interrupt controller")
>>   96303bcb401c ("irqchip/riscv-intc: Allow large non-standard interrupt number")
>>
>> on top of v6.8-rc1
>
> Sorry I missed this.  I just merged this into my testing tree, it might 
> take a bit to show up because I've managed to break my VPN so I can't 
> poke the tester box right now...

Alternatively you can just rebase on Linus tree. The interrupt changes
are already merged.

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