linux-kernel - [PATCH v9 3/3] riscv: dts: jh7110: starfive: Add timer node

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Date: Mon, 18 Mar 2024 11:06:49 +0800
From: Ziv Xu <ziv.xu@...rfivetech.com>
To: Daniel Lezcano <daniel.lezcano@...aro.org>,
	Thomas Gleixner <tglx@...utronix.de>,
	Emil Renner Berthing <emil.renner.berthing@...onical.com>,
	Christophe JAILLET <christophe.jaillet@...adoo.fr>
Cc: linux-riscv@...ts.infradead.org,
	devicetree@...r.kernel.org,
	Rob Herring <robh+dt@...nel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
	Paul Walmsley <paul.walmsley@...ive.com>,
	Palmer Dabbelt <palmer@...belt.com>,
	Albert Ou <aou@...s.berkeley.edu>,
	Philipp Zabel <p.zabel@...gutronix.de>,
	Walker Chen <walker.chen@...rfivetech.com>,
	Xingyu Wu <xingyu.wu@...rfivetech.com>,
	linux-kernel@...r.kernel.org,
	Conor Dooley <conor@...nel.org>
Subject: [PATCH v9 3/3] riscv: dts: jh7110: starfive: Add timer node

From: Xingyu Wu <xingyu.wu@...rfivetech.com>

Add the timer node for the Starfive JH7110 SoC.

Reviewed-by: Emil Renner Berthing <emil.renner.berthing@...onical.com>
Reviewed-by: Walker Chen <walker.chen@...rfivetech.com>
Signed-off-by: Xingyu Wu <xingyu.wu@...rfivetech.com>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 74ed3b9264d8..40dcceaf1f98 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -904,6 +904,26 @@
 			#gpio-cells = <2>;
 		};
 
+		timer@...50000 {
+			compatible = "starfive,jh7110-timer";
+			reg = <0x0 0x13050000 0x0 0x10000>;
+			interrupts = <69>, <70>, <71>, <72>;
+			clocks = <&syscrg JH7110_SYSCLK_TIMER_APB>,
+				 <&syscrg JH7110_SYSCLK_TIMER0>,
+				 <&syscrg JH7110_SYSCLK_TIMER1>,
+				 <&syscrg JH7110_SYSCLK_TIMER2>,
+				 <&syscrg JH7110_SYSCLK_TIMER3>;
+			clock-names = "apb", "ch0", "ch1",
+				      "ch2", "ch3";
+			resets = <&syscrg JH7110_SYSRST_TIMER_APB>,
+				 <&syscrg JH7110_SYSRST_TIMER0>,
+				 <&syscrg JH7110_SYSRST_TIMER1>,
+				 <&syscrg JH7110_SYSRST_TIMER2>,
+				 <&syscrg JH7110_SYSRST_TIMER3>;
+			reset-names = "apb", "ch0", "ch1",
+				      "ch2", "ch3";
+		};
+
 		watchdog@...70000 {
 			compatible = "starfive,jh7110-wdt";
 			reg = <0x0 0x13070000 0x0 0x10000>;
-- 
2.17.1