[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20240415225420.GD5206@sol.localdomain>
Date: Mon, 15 Apr 2024 15:54:20 -0700
From: Eric Biggers <ebiggers@...nel.org>
To: "Chang S. Bae" <chang.seok.bae@...el.com>
Cc: linux-kernel@...r.kernel.org, linux-crypto@...r.kernel.org,
dm-devel@...hat.com, luto@...nel.org, dave.hansen@...ux.intel.com,
tglx@...utronix.de, bp@...en8.de, mingo@...nel.org, x86@...nel.org,
herbert@...dor.apana.org.au, ardb@...nel.org, elliott@....com,
dan.j.williams@...el.com, bernie.keany@...el.com,
charishma1.gairuboyina@...el.com
Subject: Re: [PATCH v9 00/14] x86: Support Key Locker
On Mon, Apr 15, 2024 at 03:16:18PM -0700, Chang S. Bae wrote:
> > First, surely it's the case that in practice, all CPUs that support Key Locker
> > also support AVX? If so, then there's no need for the Key Locker assembly to
> > use legacy SSE instructions. It should instead target AVX and use VEX-coded
> > instructions. This would save some instructions and improve performance.
>
> Unfortunately, the Key Locker instructions using the AVX states were never
> implemented.
Sure, you could still use VEX-coded 128-bit instructions for everything other
than the actual AES (for example, the XTS tweak computation) though, right?
They're a bit more convenient to work with since they are non-destructive.
- Eric
Powered by blists - more mailing lists