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Message-ID: <97a6261b-7d26-4e29-88b3-1ac5084a6fc7@denx.de>
Date: Mon, 15 Apr 2024 15:24:53 +0200
From: Marek Vasut <marex@...x.de>
To: Catalin Popescu <catalin.popescu@...ca-geosystems.com>, sboyd@...nel.org,
 mturquette@...libre.com, biju.das.jz@...renesas.com,
 marek.vasut+renesas@...lbox.org
Cc: linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
 bsp-development.geo@...ca-geosystems.com, m.felsch@...gutronix.de
Subject: Re: [PATCH] clk: rs9: fix wrong default value for clock amplitude

On 4/15/24 2:42 PM, Catalin Popescu wrote:
> According to 9FGV0241, 9FGV0441 & 9FGV0841 datasheets, the default
> value for the clock amplitude is 0.8V, while the driver assumes 0.7V.
> 
> Additionally, define constants for default values for both clock
> amplitude and spread spectrum and use them.
> 
> Fixes: 892e0ddea1aa ("clk: rs9: Add Renesas 9-series PCIe clock generator driver")
> 
> Signed-off-by: Catalin Popescu <catalin.popescu@...ca-geosystems.com>

Use git send-email -v2 next time.

Reviewed-by: Marek Vasut <marex@...x.de>

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