linux-kernel - Re: [PATCH v2 cmpxchg 12/13] sh: Emulate one-byte cmpxchg

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <31ed4654-094a-4e1e-9182-973b43ae3464@app.fastmail.com>
Date: Thu, 02 May 2024 13:30:58 +0200
From: "Arnd Bergmann" <arnd@...db.de>
To: "D. Jeff Dionne" <djeffdionne@...il.com>,
 "Paul E. McKenney" <paulmck@...nel.org>
Cc: "John Paul Adrian Glaubitz" <glaubitz@...sik.fu-berlin.de>,
 Linux-Arch <linux-arch@...r.kernel.org>, linux-kernel@...r.kernel.org,
 "Marco Elver" <elver@...gle.com>,
 "Andrew Morton" <akpm@...ux-foundation.org>,
 "Thomas Gleixner" <tglx@...utronix.de>,
 "Peter Zijlstra" <peterz@...radead.org>,
 "Doug Anderson" <dianders@...omium.org>, "Petr Mladek" <pmladek@...e.com>,
 "Linus Torvalds" <torvalds@...ux-foundation.org>, kernel-team@...a.com,
 "Andi Shyti" <andi.shyti@...ux.intel.com>,
 "Palmer Dabbelt" <palmer@...osinc.com>,
 "Masami Hiramatsu" <mhiramat@...nel.org>, linux-sh@...r.kernel.org
Subject: Re: [PATCH v2 cmpxchg 12/13] sh: Emulate one-byte cmpxchg

On Thu, May 2, 2024, at 07:42, D. Jeff Dionne wrote:
> On May 2, 2024, at 14:07, Paul E. McKenney <paulmck@...nel.org> wrote:
>
>> That would be 8-bit xchg() rather than 8-byte cmpxchg(), correct?
>> 
>> Or am I missing something subtle here that makes sh also support one-byte
>> (8-bit) cmpxchg()?
>
> The native SH atomic operation is test and set TAS.B.  J2 adds a 
> compare and swap CAS.L instruction, carefully chosen for patent free 
> prior art (s360, IIRC).
>
> The (relatively expensive) encoding space we allocated for CAS.L does 
> not contain size bits.
>
> Not all SH4 patents had expired when J2 was under development, but now 
> have (watch this space).  Not sure (me myself) if there are more atomic 
> operations in sh4.

SH4A supports MIPS R4000 style LL/SC instructions, but it looks like
the older SH4 does not.

      Arnd