linux-kernel - [PATCH v2] i2c: cadence: Avoid fifo clear after start

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Date: Fri, 3 May 2024 15:12:08 +0530
From: Sai Pavan Boddu <sai.pavan.boddu@....com>
To: <linux-arm-kernel@...ts.infradead.org>, <linux-i2c@...r.kernel.org>,
	<linux-kernel@...r.kernel.org>
CC: Michal Simek <michal.simek@....com>, Andi Shyti <andi.shyti@...nel.org>,
	Lars-Peter Clausen <lars@...afoo.de>, Wolfram Sang <wsa@...nel.org>
Subject: [PATCH v2] i2c: cadence: Avoid fifo clear after start

The Driver unintentionally programs ctrl reg to clear the fifo, which
happens after the start of transaction. Previously, this was not an issue
as it involved read-modified-write. However, this issue breaks i2c reads
on QEMU, as i2c-read is executed before guest starts programming control
register.

Fixes: ff0cf7bca630 ("i2c: cadence: Remove unnecessary register reads")
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@....com>
Acked-by: Michal Simek <michal.simek@....com>
---
Changes for V2:
	Fix commit message.

 drivers/i2c/busses/i2c-cadence.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/i2c/busses/i2c-cadence.c b/drivers/i2c/busses/i2c-cadence.c
index 4bb7d6756947..2fce3e84ba64 100644
--- a/drivers/i2c/busses/i2c-cadence.c
+++ b/drivers/i2c/busses/i2c-cadence.c
@@ -633,6 +633,7 @@ static void cdns_i2c_mrecv(struct cdns_i2c *id)
 
 	if (hold_clear) {
 		ctrl_reg &= ~CDNS_I2C_CR_HOLD;
+		ctrl_reg &= ~CDNS_I2C_CR_CLR_FIFO;
 		/*
 		 * In case of Xilinx Zynq SOC, clear the HOLD bit before transfer size
 		 * register reaches '0'. This is an IP bug which causes transfer size
-- 
2.37.6