lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CAHp75VdDMOLuRhDNQ=dzoE6Yyah+k-pGm8vY8B2DmFiyPBuftw@mail.gmail.com>
Date: Tue, 14 May 2024 12:23:19 +0300
From: Andy Shevchenko <andy.shevchenko@...il.com>
To: Mark Brown <broonie@...nel.org>
Cc: Linus Walleij <linus.walleij@...aro.org>, 
	Patrick Rudolph <patrick.rudolph@...ements.com>, naresh.solanki@...ements.com, 
	linux-gpio@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] pinctrl: cy8c95x0: Cache muxed registers

On Tue, May 14, 2024 at 12:02 PM Mark Brown <broonie@...nel.org> wrote:
> On Tue, May 14, 2024 at 11:55:06AM +0300, Andy Shevchenko wrote:
>
> > It's about introducing pages of virtual registers (from regmap p.o.v.)
> > to access the banks of selectable registers. The cache most likely
> > will be the same, i.e. MAPPLE_TREE.
>
> If there's paging of registers then regmap supports this with the ranges
> feature, you can tell regmap where the window is in the physical
> register map and which register to use to switch pages and have regmap
> export the underlying registers as a linear range of virtual registers.

In this chip there are two ranges that are dependent on a selector,
one is for port selection (which the original change is about) and
another is for PWM (IIRC). Note that they are orthogonal to each
other, meaning they have their own selector registers.

-- 
With Best Regards,
Andy Shevchenko

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ