| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <db1a0b2d-1bf9-4bd4-98f5-8a38f46d6749@kernel.org>
Date: Tue, 28 May 2024 15:18:25 +0300
From: Roger Quadros <rogerq@...nel.org>
To: Siddharth Vadapalli <s-vadapalli@...com>, nm@...com, vigneshr@...com,
afd@...com, kristo@...nel.org, robh@...nel.org, krzk+dt@...nel.org,
conor+dt@...nel.org
Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, u-kumar1@...com, danishanwar@...com,
srk@...com
Subject: Re: [PATCH v3 3/7] arm64: dts: ti: k3-j722s-evm: Update USB0 and USB1
On 24/05/2024 12:05, Siddharth Vadapalli wrote:
> From: Ravi Gunasekaran <r-gunasekaran@...com>
>
> The GPIO expander on the EVM allows the USB selection for Type-C
> port to either USB0 or USB1 via USB hub. By default, let the Type-C
> port select USB0 via the GPIO expander port P05.
>
> Enable super-speed on USB1 by updating SerDes0 lane configuration.
>
> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@...com>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@...com>
> ---
> v2:
> https://lore.kernel.org/r/20240513114443.16350-4-r-gunasekaran@ti.com/
> Changes since v2:
> - Renamed serdes0_ln_ctrl to serdes_ln_ctrl corresponding to the change
> made in patch 1.
> - Dropped Serdes1 idle-states since it has not yet been added in the
> serdes_ln_ctrl node.
> - Dropped Serdes1 specific Lane-Muxing macros in "k3-serdes.h".
> - Added newline after /* J722S */ in "k3-serdes.h" following the file
> convention.
>
> v1:
> https://lore.kernel.org/r/20240429120932.11456-4-r-gunasekaran@ti.com/
> Changes since v1:
> - Removed USB aliases, line-name property for p05 GPIO hog.
> - Included k3-j722s-main.dtsi.
>
> arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 54 +++++++++++++++++++++++++
> arch/arm64/boot/dts/ti/k3-j722s.dtsi | 5 +++
> arch/arm64/boot/dts/ti/k3-serdes.h | 5 +++
> 3 files changed, 64 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> index bf3c246d13d1..a3bda39cc223 100644
> --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> @@ -9,7 +9,9 @@
> /dts-v1/;
>
> #include <dt-bindings/net/ti-dp83867.h>
> +#include <dt-bindings/phy/phy.h>
> #include "k3-j722s.dtsi"
> +#include "k3-serdes.h"
>
> / {
> compatible = "ti,j722s-evm", "ti,j722s";
> @@ -202,6 +204,12 @@ J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */
> J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */
> >;
> };
> +
> + main_usb1_pins_default: main-usb1-default-pins {
> + pinctrl-single,pins = <
> + J722S_IOPAD(0x0258, PIN_INPUT, 0) /* (B27) USB1_DRVVBUS */
> + >;
> + };
> };
>
> &cpsw3g {
> @@ -301,6 +309,13 @@ exp1: gpio@23 {
> "PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#",
> "ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN",
> "PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ";
> +
> + p05-hog {
> + /* P05 - USB2.0_MUX_SEL */
> + gpio-hog;
> + gpios = <5 GPIO_ACTIVE_LOW>;
> + output-high;
> + };
> };
> };
>
> @@ -384,3 +399,42 @@ &sdhci1 {
> status = "okay";
> bootph-all;
> };
> +
> +&serdes_ln_ctrl {
> + idle-states = <J722S_SERDES0_LANE0_USB>;
> +};
> +
> +&serdes0 {
> + status = "okay";
> + serdes0_usb_link: phy@0 {
> + reg = <0>;
> + cdns,num-lanes = <1>;
> + #phy-cells = <0>;
> + cdns,phy-type = <PHY_TYPE_USB3>;
> + resets = <&serdes_wiz0 1>;
> + };
> +};
> +
> +&usbss0 {
> + ti,vbus-divider;
> + status = "okay";
> +};
> +
> +&usb0 {
> + dr_mode = "otg";
> + usb-role-switch;
> +};
> +
> +&usbss1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_usb1_pins_default>;
> + ti,vbus-divider;
> + status = "okay";
> +};
> +
> +&usb1 {
> + dr_mode = "host";
> + maximum-speed = "super-speed";
> + phys = <&serdes0_usb_link>;
> + phy-names = "cdns3,usb3-phy";
> +};
> diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
> index c75744edb143..61b64fae1bf4 100644
> --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
> @@ -87,3 +87,8 @@ &oc_sram {
> reg = <0x00 0x70000000 0x00 0x40000>;
> ranges = <0x00 0x00 0x70000000 0x40000>;
> };
> +
> +/* Include bus peripherals that are additionally
> + * present in J722S
> + */
> + #include "k3-j722s-main.dtsi"
> diff --git a/arch/arm64/boot/dts/ti/k3-serdes.h b/arch/arm64/boot/dts/ti/k3-serdes.h
The k3-serdes.h changes should be in a separate independent patch.
> index a011ad893b44..e6a036a4e70b 100644
> --- a/arch/arm64/boot/dts/ti/k3-serdes.h
> +++ b/arch/arm64/boot/dts/ti/k3-serdes.h
> @@ -201,4 +201,9 @@
> #define J784S4_SERDES4_LANE3_USB 0x2
> #define J784S4_SERDES4_LANE3_IP4_UNUSED 0x3
>
> +/* J722S */
> +
> +#define J722S_SERDES0_LANE0_USB 0x0
> +#define J722S_SERDES0_LANE0_QSGMII_LANE2 0x1
> +
> #endif /* DTS_ARM64_TI_K3_SERDES_H */
--
cheers,
-roger
Powered by blists - more mailing lists