linux-kernel - RE: [PATCH 1/2] HID: intel-ish-hid: fix cache management mistake

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Message-ID: <DM4PR11MB599576317F5E81EE8FBD0E6093FC2@DM4PR11MB5995.namprd11.prod.outlook.com>
Date: Fri, 31 May 2024 08:51:15 +0000
From: "Zhang, Lixu" <lixu.zhang@...el.com>
To: srinivas pandruvada <srinivas.pandruvada@...ux.intel.com>, Arnd Bergmann
	<arnd@...db.de>, Arnd Bergmann <arnd@...nel.org>, Jiri Kosina
	<jikos@...nel.org>, Benjamin Tissoires <bentiss@...nel.org>, "Xu, Even"
	<even.xu@...el.com>
CC: "linux-input@...r.kernel.org" <linux-input@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH 1/2] HID: intel-ish-hid: fix cache management mistake

>-----Original Message-----
>From: Zhang, Lixu
>Sent: Thursday, May 30, 2024 3:42 PM
>To: srinivas pandruvada <srinivas.pandruvada@...ux.intel.com>; Arnd
>Bergmann <arnd@...db.de>; Arnd Bergmann <arnd@...nel.org>; Jiri Kosina
><jikos@...nel.org>; Benjamin Tissoires <bentiss@...nel.org>; Xu, Even
><even.xu@...el.com>
>Cc: linux-input@...r.kernel.org; linux-kernel@...r.kernel.org
>Subject: RE: [PATCH 1/2] HID: intel-ish-hid: fix cache management mistake
>
>>-----Original Message-----
>>From: srinivas pandruvada <srinivas.pandruvada@...ux.intel.com>
>>Sent: Thursday, May 30, 2024 6:25 AM
>>To: Arnd Bergmann <arnd@...db.de>; Zhang, Lixu <lixu.zhang@...el.com>;
>>Arnd Bergmann <arnd@...nel.org>; Jiri Kosina <jikos@...nel.org>;
>>Benjamin Tissoires <bentiss@...nel.org>
>>Cc: linux-input@...r.kernel.org; linux-kernel@...r.kernel.org
>>Subject: Re: [PATCH 1/2] HID: intel-ish-hid: fix cache management
>>mistake
>>
>>On Wed, 2024-05-29 at 09:06 +0200, Arnd Bergmann wrote:
>>> On Wed, May 29, 2024, at 08:46, Zhang, Lixu wrote:
>>> > >
>>> >
>>> > > +		dma_wmb();
>>> > I tested it on the platform, but it didn't wok.
>>> >
>>>
>>> What behavior do you see instead?
>Hi Arnd, please refer to the information below.
>
>>> If the manual cache flush works
>>> around a bug, that would indicate that the device itself is not
>>> coherent and the dma_alloc_coherent() in the architecture is broken.
>>
Hi Arnd,

Flush cache is necessary for some performance reason on this device.

Thanks,
Lixu