Message-ID: <243098a9-296b-4cbc-9f48-d37ab3b94153@arm.com>
Date: Tue, 18 Jun 2024 10:47:31 +0100
From: Suzuki K Poulose <suzuki.poulose@....com>
To: Jie Gan <quic_jiegan@...cinc.com>,
 Mathieu Poirier <mathieu.poirier@...aro.org>,
 Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
 Konrad Dybcio <konradybcio@...il.com>, Mike Leach <mike.leach@...aro.org>,
 Rob Herring <robh+dt@...nel.org>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>
Cc: Jinlong Mao <quic_jinlmao@...cinc.com>,
 Greg Kroah-Hartman <gregkh@...uxfoundation.org>, coresight@...ts.linaro.org,
 linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
 devicetree@...r.kernel.org, Tingwei Zhang <quic_tingweiz@...cinc.com>,
 Yuanfang Zhang <quic_yuanfang@...cinc.com>,
 Tao Zhang <quic_taozha@...cinc.com>, Trilok Soni <quic_tsoni@...cinc.com>,
 Song Chai <quic_songchai@...cinc.com>, linux-arm-msm@...r.kernel.org,
 andersson@...nel.org, quic_yijiyang@...cinc.com, quic_yuanjiey@...cinc.com,
 quic_liuxin@...cinc.com, quic_yanzl@...cinc.com, quic_xinlon@...cinc.com,
 quic_xueqnie@...cinc.com, quic_sijiwu@...cinc.com
Subject: Re: [PATCH v1 0/3] Add coresight slave register driver to support
 data filter function

On 18/06/2024 08:27, Jie Gan wrote:
> The Coresight Slave Register(CSR) device hosts miscellaneous configuration
> registers to control various features related to TMC ETR device.
> 
> The CSR device works as a helper device physically connected to the TMC ETR device.
> ---------------------------------------------------------
>               |ETR0|             |ETR1|
>                . \                 / .
>                .  \               /  .
>                .   \             /   .
>                .    \           /    .
> ---------------------------------------------------
> ETR0ATID0-ETR0ATID3     CSR     ETR1ATID0-ETR1ATID3
> ---------------------------------------------------
> Each ETR has four ATID registers with 128 bits long in total.
> e.g. ETR0ATID0-ETR0ATID3 registers are used by ETR0 device.

What is the maximum number of connections possible for CSR ? 2 ETRs ?

> 
> Based on the trace id which is programed in CSR ATID register of
> specific ETR, trace data with that trace id can get into ETR's buffer

How do you handle cases where there are multiple TraceIDs in a the 
stream ? e.g., perf tracing a multi-threaded app ? Each ETM will have
a distinct traceid. Is there way to disable filtering by CSR ?

Side note, with James's trace id allocation per sink series makes this
easier for the ETR to know the trace ids allocated for the current
session. Works only for perf though.


> while other trace data gets ignored. CSR may contain several ATID registers.
> Each ATID register is associated with an ETR device.
> 
> To achieve this function, the trace id is obtained and stored in the related
> ETR device's driver data just before enabling the CSR. Then, the CSR
> device can easily obtain the trace ID from the ETR's driver data because the
> ETR's driver data is passed to the CSR's enable/disable functions.
> 
> Ensure that every source device has already allocated a trace ID in its probe
> session because the sink device should always be the first device to

How is that possible ? We are going backwards in the trace id allocation
with your proposal. What is the purpose of this hardware when you could 
use a replicator with trace filtering based on masks ?

> enable when operating coresight_enable_path function. As a helper device of the
> ETR, the CSR device will program the ATID register of a specific ETR according to
> the trace id to enable data filter function at a very early stage. Without the
> correct trace ID, the enablement session will not work.
> 
> Each CSR's enable session will set one bit in the ATID register.

So is this a bitmap of "enable/disable" ATID ? I really don't see the
usecase of the CSR "device" yet. Please could you share "usecase" ?

Suzuki


> Every CSR's disbale seesion will reset all bits of the ATID register.
> 
> This patch only supports sysfs mode. I will send the perf mode part patch
> once it is ready.
> 
> Looking forward to receiving comments as this is a new driver.
> 
> Thanks!
> 
> Jie Gan (3):
>    dt-bindings: arm: Add binding document for Coresight Slave Register
>      device.
>    coresight: Add coresight slave register driver to support data filter
>      function in sysfs mode
>    arm64: dts: qcom: Add CSR and ETR nodes for SA8775p
> 
>   .../bindings/arm/arm,coresight-tmc.yaml       |   8 +
>   .../bindings/arm/qcom,coresight-csr.yaml      |  49 +++
>   arch/arm64/boot/dts/qcom/sa8775p.dtsi         | 167 ++++++++++
>   drivers/hwtracing/coresight/Kconfig           |   6 +
>   drivers/hwtracing/coresight/Makefile          |   1 +
>   drivers/hwtracing/coresight/coresight-core.c  |   6 +-
>   drivers/hwtracing/coresight/coresight-csr.c   | 315 ++++++++++++++++++
>   drivers/hwtracing/coresight/coresight-csr.h   |  24 ++
>   .../coresight/coresight-etm4x-core.c          |   1 +
>   drivers/hwtracing/coresight/coresight-stm.c   |  50 ---
>   drivers/hwtracing/coresight/coresight-sysfs.c |  45 ++-
>   .../hwtracing/coresight/coresight-tmc-core.c  |   1 +
>   drivers/hwtracing/coresight/coresight-tmc.h   |   2 +
>   include/linux/coresight-stm.h                 |  44 +++
>   14 files changed, 665 insertions(+), 54 deletions(-)
>   create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-csr.yaml
>   create mode 100644 drivers/hwtracing/coresight/coresight-csr.c
>   create mode 100644 drivers/hwtracing/coresight/coresight-csr.h
> 

Powered by blists - more mailing lists