linux-kernel - Re: [PATCH v1 1/3] dt-bindings: arm: Add binding document for Coresight Slave Register device.

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Date: Tue, 18 Jun 2024 10:56:16 +0100
From: Suzuki K Poulose <suzuki.poulose@....com>
To: Jie Gan <quic_jiegan@...cinc.com>,
 Mathieu Poirier <mathieu.poirier@...aro.org>,
 Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
 Konrad Dybcio <konradybcio@...il.com>, Mike Leach <mike.leach@...aro.org>,
 Rob Herring <robh+dt@...nel.org>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>
Cc: Jinlong Mao <quic_jinlmao@...cinc.com>,
 Greg Kroah-Hartman <gregkh@...uxfoundation.org>, coresight@...ts.linaro.org,
 linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
 devicetree@...r.kernel.org, Tingwei Zhang <quic_tingweiz@...cinc.com>,
 Yuanfang Zhang <quic_yuanfang@...cinc.com>,
 Tao Zhang <quic_taozha@...cinc.com>, Trilok Soni <quic_tsoni@...cinc.com>,
 Song Chai <quic_songchai@...cinc.com>, linux-arm-msm@...r.kernel.org,
 andersson@...nel.org, quic_yijiyang@...cinc.com, quic_yuanjiey@...cinc.com,
 quic_liuxin@...cinc.com, quic_yanzl@...cinc.com, quic_xinlon@...cinc.com,
 quic_xueqnie@...cinc.com, quic_sijiwu@...cinc.com
Subject: Re: [PATCH v1 1/3] dt-bindings: arm: Add binding document for
 Coresight Slave Register device.

On 18/06/2024 08:27, Jie Gan wrote:
> Add binding document for Coresight Slave Register device.

Is this a made up name of the driver ? CoreSight Slave Register
device sounds nowhere near to what it does. If you have a proper
name for the "IP" please use that.

> 
> Add a new property to TMC, qcom,csr-atid-offset, to indicate which
> ATID registers will be used by the TMC ETR. Each TMC ETR device is
> associated with four ATID registers that are continuous in address.
> 
> Signed-off-by: Jie Gan <quic_jiegan@...cinc.com>
> ---
>   .../bindings/arm/arm,coresight-tmc.yaml       |  8 ++
>   .../bindings/arm/qcom,coresight-csr.yaml      | 76 +++++++++++++++++++
>   2 files changed, 84 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-csr.yaml
> 
> diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml
> index cb8dceaca70e..295641a96c21 100644
> --- a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml
> +++ b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml
> @@ -82,6 +82,14 @@ properties:
>       $ref: /schemas/types.yaml#/definitions/uint32
>       maximum: 15
>   
> +  qcom,csr-atid-offset:
> +    description:
> +      Offset to the coresight slave register component's ATID register
> +      that is used by specific TMC ETR. The ATID register can be programed according
> +      to the trace id to filter out specific trace data which gets through the ETR
> +      to the downstream components.
> +    $ref: /schemas/types.yaml#/definitions/uint32

Why do we need this ? Could this not be inferred from the "input port" 
to which this ETR is connected on the CSR ?

e.g., input-0 : Offset 0
       input-1 : Offset for Bank1




> +
>     in-ports:
>       $ref: /schemas/graph.yaml#/properties/ports
>       additionalProperties: false
> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-csr.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-csr.yaml
> new file mode 100644
> index 000000000000..16f97cbe3d4b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-csr.yaml
> @@ -0,0 +1,76 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/qcom,coresight-csr.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: CoreSight Slave Register
> +
> +maintainers:
> +  - Yuanfang Zhang <quic_yuanfang@...cinc.com>
> +  - Mao Jinlong <quic_jinlmao@...cinc.com>
> +  - Jie Gan <quic_jiegan@...cinc.com>
> +
> +description:
> +  The Coresight Slave Register controls various Coresight behaviors.
> +  Used to enable/disable ETR’s data filter function based on trace ID.
> +
> +properties:
> +  compatible:
> +    const: qcom,coresight-csr
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +  clock-names:
> +    maxItems: 1
> +    items:
> +      - const: apb_pclk
> +
> +  reg-names:
> +    items:
> +      - const: csr-base
> +
> +  in-ports:
> +    $ref: /schemas/graph.yaml#/properties/ports
> +
> +    patternProperties:
> +      '^port(@[0-7])?$':
> +        description: Input connections from CoreSight Trace bus
> +        $ref: /schemas/graph.yaml#/properties/port
> +
> +required:
> +  - compatible
> +  - reg
> +  - in-ports
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    syscon@...01000 {
> +        compatible = "qcom,coresight-csr";
> +        reg = <0x0 0x10001000 0x0 0x1000>;
> +        reg-names = "csr-base";
> +
> +        in-ports {
> +            #address-cells = <1>;
> +            #size-cells = <0>;
> +
> +            port@0 {
> +                reg = <0>;
> +                csr_in_port0: endpoint {
> +                    remote-endpoint = <&etr0_out_port>;
> +                };
> +            };
> +
> +            port@1 {
> +                reg = <1>;
> +                csr_in_port1: endpoint {
> +                    remote-endpoint = <&etr1_out_port>;
> +                };
> +            };
> +        };
> +    };