linux-kernel - Re: Re: [PATCH] PCI: Enable io space 1k granularity for intel cpu root port

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Date: Sat, 22 Jun 2024 23:06:18 +0800
From: "zhoushengqing@...info.com" <zhoushengqing@...info.com>
To: "Bjorn Helgaas" <helgaas@...nel.org>
Cc: "Bjorn Helgaas" <bhelgaas@...gle.com>, 
	linux-pci <linux-pci@...r.kernel.org>, 
	linux-kernel <linux-kernel@...r.kernel.org>, 
	zhoushengqing <zhoushengqing@...info.com>
Subject: Re: Re: [PATCH] PCI: Enable io space 1k granularity for intel cpu root port

>> This patch add 1k granularity for intel root port bridge.Intel latest



>> server CPU support 1K granularity,And there is an BIOS setup item named



>> "EN1K",but linux doesn't support it. if an IIO has 5 IOU (SPR has 5 IOUs)



>> all are bifurcated 2x8.In a 2P server system,There are 20 P2P bridges



>> present.if keep 4K granularity allocation,it need 20*4=80k io space,



>> exceeding 64k.I test it in a 16*nvidia 4090s system under intel eaglestrem



>> platform.There are six 4090s that cannot be allocated I/O resources.



>> So I applied this patch.And I found a similar implementation in quirks.c,



>> but it only targets the Intel P64H2 platform.



>>



>> Signed-off-by: Zhou Shengqing <zhoushengqing@...info.com>



>> ---



>>  drivers/pci/probe.c | 22 ++++++++++++++++++++++



>>  1 file changed, 22 insertions(+)



>>



>> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c



>> index 5fbabb4e3425..3f0c901c6653 100644



>> --- a/drivers/pci/probe.c



>> +++ b/drivers/pci/probe.c



>> @@ -461,6 +461,8 @@ static void pci_read_bridge_windows(struct pci_dev *bridge)



>>  u32 buses;



>>  u16 io;



>>  u32 pmem, tmp;



>> + u16 ven_id, dev_id;



>> + u16 en1k = 0;



>>  struct resource res;



>>



>>  pci_read_config_dword(bridge, PCI_PRIMARY_BUS, &buses);



>> @@ -478,6 +480,26 @@ static void pci_read_bridge_windows(struct pci_dev *bridge)



>>  }



>>  if (io) {



>>  bridge->io_window = 1;



>> + if (pci_is_root_bus(bridge->bus)) {



>> + list_for_each_entry(dev, &bridge->bus->devices, bus_list) {



>> + pci_read_config_word(dev, PCI_VENDOR_ID, &ven_id);



>> + pci_read_config_word(dev, PCI_DEVICE_ID, &dev_id);



>> + if (ven_id == PCI_VENDOR_ID_INTEL && dev_id == 0x09a2) {



>> + /*IIO MISC Control offset 0x1c0*/



>> + pci_read_config_word(dev, 0x1c0, &en1k);



>> + }



>> + }



>> + /*



>> + *Intel ICX SPR EMR GNR



>> + *IIO MISC Control (IIOMISCCTRL_1_5_0_CFG) — Offset 1C0h



>> + *bit 2:Enable 1K (EN1K)



>> + *This bit when set, enables 1K granularity for I/O space decode



>> + *in each of the virtual P2P bridges



>> + *corresponding to root ports, and DMI ports.



>> + */



>> + if (en1k & 0x4)



>> + bridge->io_window_1k = 1;



>> + }



>



>Can you implement this as a quirk similar to quirk_p64h2_1k_io()?



>



>I don't want to clutter the generic code with device-specific things



>like this.




I have attempted to implement this patch in quirks.c.But there doesn't seem



to be a suitable DECLARE_PCI_FIXUP* to do this.because the patch is not targeting



the device itself, It targets other P2P devices with the same bus number.



Any other suggestions? Thanks.


>



>>  pci_read_bridge_io(bridge, &res, true);



>>  }



>>



>> --



>> 2.39.2



>>



> 



> --



> 2.39.2



>