linux-kernel - Re: [PATCH 1/5] clk: qcom: dispcc-sm8650: Park RCG's clk source at XO during disable

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <c59a50e1-5d06-4d8c-98ab-4a86c7b821de@linaro.org>
Date: Mon, 24 Jun 2024 09:54:57 +0200
From: Neil Armstrong <neil.armstrong@...aro.org>
To: Taniya Das <quic_tdas@...cinc.com>, Bjorn Andersson
 <andersson@...nel.org>, Michael Turquette <mturquette@...libre.com>,
 Stephen Boyd <sboyd@...nel.org>, Konrad Dybcio <konrad.dybcio@...aro.org>
Cc: linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
 linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/5] clk: qcom: dispcc-sm8650: Park RCG's clk source at XO
 during disable

On 21/06/2024 18:56, Taniya Das wrote:
> 
> 
> On 6/21/2024 7:31 PM, Neil Armstrong wrote:
>> The RCG's clk src has to be parked at XO while disabling as per the
>> HW recommendation, hence use clk_rcg2_shared_ops to achieve the same.
>>
>> Fixes: 9e939f008338 ("clk: qcom: add the SM8650 Display Clock Controller driver")
>> Signed-off-by: Neil Armstrong <neil.armstrong@...aro.org>
>> ---
>>   drivers/clk/qcom/dispcc-sm8650.c | 16 ++++++++--------
>>   1 file changed, 8 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/clk/qcom/dispcc-sm8650.c b/drivers/clk/qcom/dispcc-sm8650.c
>> index c9d2751f5cb8..31c82f791b44 100644
>> --- a/drivers/clk/qcom/dispcc-sm8650.c
>> +++ b/drivers/clk/qcom/dispcc-sm8650.c
>> @@ -339,7 +339,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = {
>>           .parent_data = disp_cc_parent_data_0,
>>           .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
>>           .flags = CLK_SET_RATE_PARENT,
>> -        .ops = &clk_rcg2_ops,
>> +        .ops = &clk_rcg2_shared_ops,
>>       },
>>   };
>> @@ -457,7 +457,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = {
>>           .parent_data = disp_cc_parent_data_0,
>>           .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
>>           .flags = CLK_SET_RATE_PARENT,
>> -        .ops = &clk_rcg2_ops,
>> +        .ops = &clk_rcg2_shared_ops,
>>       },
>>   };
>> @@ -516,7 +516,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = {
>>           .parent_data = disp_cc_parent_data_0,
>>           .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
>>           .flags = CLK_SET_RATE_PARENT,
>> -        .ops = &clk_rcg2_ops,
>> +        .ops = &clk_rcg2_shared_ops,
>>       },
>>   };
>> @@ -560,7 +560,7 @@ static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
>>           .parent_data = disp_cc_parent_data_5,
>>           .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
>>           .flags = CLK_SET_RATE_PARENT,
>> -        .ops = &clk_rcg2_ops,
>> +        .ops = &clk_rcg2_shared_ops,
>>       },
>>   };
>> @@ -575,7 +575,7 @@ static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
>>           .parent_data = disp_cc_parent_data_5,
>>           .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
>>           .flags = CLK_SET_RATE_PARENT,
>> -        .ops = &clk_rcg2_ops,
>> +        .ops = &clk_rcg2_shared_ops,
>>       },
>>   };
>> @@ -647,7 +647,7 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
>>           .parent_data = disp_cc_parent_data_0,
>>           .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
>>           .flags = CLK_SET_RATE_PARENT,
>> -        .ops = &clk_rcg2_ops,
>> +        .ops = &clk_rcg2_shared_ops,
>>       },
>>   };
>> @@ -667,7 +667,7 @@ static struct clk_rcg2 disp_cc_sleep_clk_src = {
>>           .parent_data = disp_cc_parent_data_9,
>>           .num_parents = ARRAY_SIZE(disp_cc_parent_data_9),
>>           .flags = CLK_SET_RATE_PARENT,
>> -        .ops = &clk_rcg2_ops,
>> +        .ops = &clk_rcg2_shared_ops,
>>       },
> Technically not required for this RCG as the source is sleep clock.

Ack

>>   };
>> @@ -682,7 +682,7 @@ static struct clk_rcg2 disp_cc_xo_clk_src = {
>>           .parent_data = disp_cc_parent_data_0_ao,
>>           .num_parents = ARRAY_SIZE(disp_cc_parent_data_0_ao),
>>           .flags = CLK_SET_RATE_PARENT,
>> -        .ops = &clk_rcg2_ops,
>> +        .ops = &clk_rcg2_shared_ops,
>>       },
>>   };
> This RCG supports only XO frequency and can be ignored.

Ack,

Thx,
Neil

>>
>