linux-kernel - Re: linux-next: manual merge of the tip tree with the pm tree

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Date: Tue, 25 Jun 2024 11:00:26 +0800
From: Xiaojian Du <xiaojidu@....com>
To: Mark Brown <broonie@...nel.org>, Thomas Gleixner <tglx@...utronix.de>,
 Ingo Molnar <mingo@...hat.com>, "H. Peter Anvin" <hpa@...or.com>,
 Peter Zijlstra <peterz@...radead.org>
Cc: Borislav Petkov <bp@...en8.de>,
 Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
 Linux Next Mailing List <linux-next@...r.kernel.org>,
 Mario Limonciello <mario.limonciello@....com>,
 Perry Yuan <perry.yuan@....com>, Xiaojian Du <Xiaojian.Du@....com>
Subject: Re: linux-next: manual merge of the tip tree with the pm tree

Hi Mark,

Many thanks for your help.

On 2024/6/25 1:06, Mark Brown wrote:
> Hi all,
>
> Today's linux-next merge of the tip tree got a conflict in:
>
>    arch/x86/include/asm/cpufeatures.h
>
> between commit:
>
>    c7107750b2ffa ("x86/cpufeatures: Add AMD FAST CPPC feature flag")
>
> from the pm tree and commit:
>
>    78ce84b9e0a54 ("x86/cpufeatures: Flip the /proc/cpuinfo appearance logic")
>
> from the tip tree.
>
> I fixed it up (see below) and can carry the fix as necessary. This
> is now fixed as far as linux-next is concerned, but any non trivial
> conflicts should be mentioned to your upstream maintainer when your tree
> is submitted for merging.  You may also want to consider cooperating
> with the maintainer of the conflicting tree to minimise any particularly
> complex conflicts.
>
> diff --cc arch/x86/include/asm/cpufeatures.h
> index 6c128d463a143,6007462e03d66..0000000000000
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@@ -465,12 -466,11 +466,12 @@@
>     *
>     * Reuse free bits when adding new feature flags!
>     */
> - #define X86_FEATURE_AMD_LBR_PMC_FREEZE	(21*32+ 0) /* AMD LBR and PMC Freeze */
> - #define X86_FEATURE_CLEAR_BHB_LOOP	(21*32+ 1) /* "" Clear branch history at syscall entry using SW loop */
> - #define X86_FEATURE_BHI_CTRL		(21*32+ 2) /* "" BHI_DIS_S HW control available */
> - #define X86_FEATURE_CLEAR_BHB_HW	(21*32+ 3) /* "" BHI_DIS_S HW control enabled */
> - #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* "" Clear branch history at vmexit using SW loop */
> - #define X86_FEATURE_FAST_CPPC		(21*32 + 5) /* "" AMD Fast CPPC */
> + #define X86_FEATURE_AMD_LBR_PMC_FREEZE	(21*32+ 0) /* "amd_lbr_pmc_freeze" AMD LBR and PMC Freeze */
> + #define X86_FEATURE_CLEAR_BHB_LOOP	(21*32+ 1) /* Clear branch history at syscall entry using SW loop */
> + #define X86_FEATURE_BHI_CTRL		(21*32+ 2) /* BHI_DIS_S HW control available */
> + #define X86_FEATURE_CLEAR_BHB_HW	(21*32+ 3) /* BHI_DIS_S HW control enabled */
> + #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch history at vmexit using SW loop */
> ++#define X86_FEATURE_FAST_CPPC		(21*32 + 5) /* AMD Fast CPPC */
>    

But it is better to hide this new flag "Fast CPPC", prefer to use " /* 
"" AMD Fast CPPC */ ".
Not expected that "CPPC" and "Fast CPPC" are listed to user at the same 
time, it will cause confusion.

Thanks,
Xiaojian

>    /*
>     * BUG word(s)