linux-kernel - Re: [PATCH 1/1] iommu/riscv: Support sharing irq lines between iommu queues

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date: Mon, 1 Jul 2024 10:47:18 +0200
From: Tomasz Jeznach <tjeznach@...osinc.com>
To: Xu Lu <luxu.kernel@...edance.com>
Cc: joro@...tes.org, will@...nel.org, robin.murphy@....com, 
	paul.walmsley@...ive.com, palmer@...belt.com, aou@...s.berkeley.edu, 
	apatel@...tanamicro.com, sunilvl@...tanamicro.com, iommu@...ts.linux.dev, 
	linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org, 
	linux@...osinc.com, baolu.lu@...ux.intel.com, lihangjing@...edance.com, 
	xieyongji@...edance.com
Subject: Re: [PATCH 1/1] iommu/riscv: Support sharing irq lines between iommu queues

On Mon, Jul 1, 2024 at 9:29 AM 'Xu Lu' via linux <linux@...osinc.com> wrote:
>
> When the number of wired interrupt lines is less than the number of
> iommu queues, we should assign one irq line for several queues and
> configure csr icvec accordingly.
>

Is this case not already covered by the code in function
riscv_iommu_init_check(), assigning cause to vector register (ICVEC)
based on available interrupt vectors? Interrupt vector selection is
based on accepted ICVEC configuration (see riscv_iommu_queue_vec()).

Relevant code (patch 'Command and fault queue support'):
iommu->icvec = FIELD_PREP(RISCV_IOMMU_ICVEC_FIV, 1 % iommu->irqs_count) |
       FIELD_PREP(RISCV_IOMMU_ICVEC_PIV, 2 % iommu->irqs_count) |
       FIELD_PREP(RISCV_IOMMU_ICVEC_PMIV, 3 % iommu->irqs_count);

Values in iommu->irqs[] should represent actual interrupts allocated
for the device.

Best,
- Tomasz

> Signed-off-by: Xu Lu <luxu.kernel@...edance.com>
> ---
>  drivers/iommu/riscv/iommu-platform.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/drivers/iommu/riscv/iommu-platform.c b/drivers/iommu/riscv/iommu-platform.c
> index da336863f152..1d0af1260d5b 100644
> --- a/drivers/iommu/riscv/iommu-platform.c
> +++ b/drivers/iommu/riscv/iommu-platform.c
> @@ -60,6 +60,10 @@ static int riscv_iommu_platform_probe(struct platform_device *pdev)
>         for (vec = 0; vec < iommu->irqs_count; vec++)
>                 iommu->irqs[vec] = platform_get_irq(pdev, vec);
>
> +       for (vec = iommu->irqs_count; vec < RISCV_IOMMU_INTR_COUNT; vec++)
> +               iommu->irqs[vec] = platform_get_irq(pdev,
> +                                                   (vec % iommu->irqs_count));
> +
>         /* Enable wire-signaled interrupts, fctl.WSI */
>         if (!(iommu->fctl & RISCV_IOMMU_FCTL_WSI)) {
>                 iommu->fctl |= RISCV_IOMMU_FCTL_WSI;
> --
> 2.20.1
>
> --
> You received this message because you are subscribed to the Google Groups "linux" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux+unsubscribe@...osinc.com.
> To view this discussion on the web visit https://groups.google.com/a/rivosinc.com/d/msgid/linux/20240701072908.25503-2-luxu.kernel%40bytedance.com.
> For more options, visit https://groups.google.com/a/rivosinc.com/d/optout.