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Message-Id: <20240821085644.240009-7-prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: Wed, 21 Aug 2024 09:56:42 +0100
From: Prabhakar <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert+renesas@...der.be>,
Magnus Damm <magnus.damm@...il.com>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: linux-renesas-soc@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Prabhakar <prabhakar.csengg@...il.com>,
Biju Das <biju.das.jz@...renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: [PATCH v3 6/8] arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Add WDT0-WDT3 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
---
v2->v3
- Grouped WDT nodes
v1->v2
- New patch
---
arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 44 ++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 9103335ac583..fb911780c4b4 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -201,6 +201,50 @@ ostm3: timer@...01000 {
status = "disabled";
};
+ wdt0: watchdog@...00400 {
+ compatible = "renesas,r9a09g057-wdt";
+ reg = <0 0x11c00400 0 0x400>;
+ clocks = <&cpg CPG_MOD 75>,
+ <&cpg CPG_MOD 76>;
+ clock-names = "pclk", "oscclk";
+ resets = <&cpg 117>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ wdt2: watchdog@...00000 {
+ compatible = "renesas,r9a09g057-wdt";
+ reg = <0 0x13000000 0 0x400>;
+ clocks = <&cpg CPG_MOD 79>,
+ <&cpg CPG_MOD 80>;
+ clock-names = "pclk", "oscclk";
+ resets = <&cpg 119>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ wdt3: watchdog@...00400 {
+ compatible = "renesas,r9a09g057-wdt";
+ reg = <0 0x13000400 0 0x400>;
+ clocks = <&cpg CPG_MOD 81>,
+ <&cpg CPG_MOD 82>;
+ clock-names = "pclk", "oscclk";
+ resets = <&cpg 120>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ wdt1: watchdog@...00000 {
+ compatible = "renesas,r9a09g057-wdt";
+ reg = <0 0x14400000 0 0x400>;
+ clocks = <&cpg CPG_MOD 77>,
+ <&cpg CPG_MOD 78>;
+ clock-names = "pclk", "oscclk";
+ resets = <&cpg 118>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
i2c8: i2c@...01000 {
compatible = "renesas,riic-r9a09g057";
reg = <0 0x11c01000 0 0x400>;
--
2.34.1
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