linux-kernel - Re: [PATCH v2 4/5] efi/cper: align ARM CPER type with UEFI 2.9A/2.10 specs

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Message-ID: <20240904064549.0bddeaab@foz.lan>
Date: Wed, 4 Sep 2024 06:45:49 +0200
From: Mauro Carvalho Chehab <mchehab+huawei@...nel.org>
To: Borislav Petkov <bp@...en8.de>
Cc: Tony Luck <tony.luck@...el.com>, Ard Biesheuvel <ardb@...nel.org>, James
 Morse <james.morse@....com>, Jonathan Cameron
 <Jonathan.Cameron@...wei.com>, Len Brown <lenb@...nel.org>, "Rafael J.
 Wysocki" <rafael@...nel.org>, Shiju Jose <shiju.jose@...wei.com>, Alison
 Schofield <alison.schofield@...el.com>, Dan Williams
 <dan.j.williams@...el.com>, Daniel Ferguson
 <danielf@...amperecomputing.com>, Dave Jiang <dave.jiang@...el.com>, Ira
 Weiny <ira.weiny@...el.com>, Shuai Xue <xueshuai@...ux.alibaba.com>,
 linux-acpi@...r.kernel.org, linux-edac@...r.kernel.org,
 linux-efi@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 4/5] efi/cper: align ARM CPER type with UEFI
 2.9A/2.10 specs

Em Mon, 2 Sep 2024 17:27:55 +0200
Borislav Petkov <bp@...en8.de> escreveu:

> On Thu, Jul 11, 2024 at 08:28:55AM +0200, Mauro Carvalho Chehab wrote:
> > Up to UEFI spec 2.9, the type byte of CPER struct for ARM processor
> > was defined simply as:
> > 
> > Type at byte offset 4:
> > 
> > 	- Cache error
> > 	- TLB Error
> > 	- Bus Error
> > 	- Micro-architectural Error
> > 	All other values are reserved
> > 
> > Yet, there was no information about how this would be encoded.
> > 
> > Spec 2.9A errata corrected it by defining:
> > 
> > 	- Bit 1 - Cache Error
> > 	- Bit 2 - TLB Error
> > 	- Bit 3 - Bus Error
> > 	- Bit 4 - Micro-architectural Error
> > 	All other values are reserved
> > 
> > That actually aligns with the values already defined on older
> > versions at N.2.4.1. Generic Processor Error Section.
> > 
> > Spec 2.10 also preserve the same encoding as 2.9A.
> > 
> > Adjust CPER and GHES handling code for both generic and ARM
> > processors to properly handle UEFI 2.9A and 2.10 encoding.
> > 
> > Link: https://uefi.org/specs/UEFI/2.10/Apx_N_Common_Platform_Error_Record.html#arm-processor-error-information
> > Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@...nel.org>
> > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@...wei.com>
> > ---
> >  drivers/acpi/apei/ghes.c        | 15 ++++++----
> >  drivers/firmware/efi/cper-arm.c | 50 ++++++++++++++++-----------------
> >  include/linux/cper.h            | 10 +++----
> >  3 files changed, 38 insertions(+), 37 deletions(-)  
> 
> How was this thing ever tested?!?!

It was tested on ARM, together with QEMU error injection code I'm working
there. Currently, only GPIO and SEA notification types are supported, so
no x86 support yet (I'm trying to add SCI too, allowing to test on x86
as well[1]).

It sounds that bitfield.h is indirectly included from
arch/arm64/include/asm/sysreg.h when compiled on such arch.

Anyway, I'll add an include for it there.

[1] https://gitlab.com/mchehab_kernel/qemu/-/commits/TODO_x86_ghes?ref_type=heads
    code is not working yet. I'm stuck with an issue related with EDK2.
    on x86_64, it is failing to create a new fw_cfg file needed to
    store HEST error structures.

Regards,
Mauro