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Message-ID: <ZuvmIG5h2hnicIjQ@finisterre.sirena.org.uk>
Date: Thu, 19 Sep 2024 10:51:44 +0200
From: Mark Brown <broonie@...nel.org>
To: Raju Rangoju <Raju.Rangoju@....com>
Cc: linux-spi@...r.kernel.org, linux-kernel@...r.kernel.org,
	sanju.mehta@....com, krishnamoorthi.m@....com,
	akshata.mukundshetty@....com
Subject: Re: [PATCH 7/9] spi: spi_amd: Enhance SPI-MEM support functions

On Wed, Sep 18, 2024 at 04:20:35PM +0530, Raju Rangoju wrote:

> AMD SPI0 controller supports quad mode only for read operations and has
> limited support for quad mode writes. And, the AMD HID2 SPI controller
> supports DMA read, allowing for up to 4 KB of data to be read in single
> transaction. Update the SPI-MEM support functions to reflect these hardware
> capabilities.

>  	/* bus width is number of IO lines used to transmit */
> -	if (op->cmd.buswidth > 1 || op->addr.buswidth > 4 ||
> -	    op->data.buswidth > 4 || op->data.nbytes > AMD_SPI_MAX_DATA)

So this code you added earlier in the series is clearly buggy...  this
whole change should've been part of that patch, and the addidion of the
patch adding the new HID.

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