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Message-ID: <ff19fa23-7846-654a-b1c2-e95bdd1adf36@amd.com>
Date: Tue, 24 Sep 2024 20:53:32 +0530
From: "Rangoju, Raju" <raju.rangoju@....com>
To: Mark Brown <broonie@...nel.org>
Cc: linux-spi@...r.kernel.org, linux-kernel@...r.kernel.org,
 sanju.mehta@....com, krishnamoorthi.m@....com, akshata.mukundshetty@....com
Subject: Re: [PATCH 2/9] spi: spi_amd: Enable dual and quad I/O modes



On 9/19/2024 2:13 PM, Mark Brown wrote:
> On Wed, Sep 18, 2024 at 04:20:30PM +0530, Raju Rangoju wrote:
> 
>>   {
>>   	/* bus width is number of IO lines used to transmit */
>> -	if (op->cmd.buswidth > 1 || op->addr.buswidth > 1 ||
>> -	    op->data.buswidth > 1 || op->data.nbytes > AMD_SPI_MAX_DATA)
>> +	if (op->cmd.buswidth > 1 || op->addr.buswidth > 4 ||
>> +	    op->data.buswidth > 4 || op->data.nbytes > AMD_SPI_MAX_DATA)
>>   		return false;
> 
> I'm not seeing anything where we tell the hardware about the width?

The hardware already supports single, dual, and quad I/O modes, and this 
functionality is enabled by default. No explicit software configuration 
is necessary to select the desired I/O mode. The hardware will 
automatically determine the appropriate mode based on the programmed 
opcode. This current patch is only intended to communicate these 
hardware capabilities to upper layers.


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