linux-kernel - RE: [PATCH v4 02/10] x86/cpu/topology: Add CPU type to struct cpuinfo

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Message-ID: <SJ1PR11MB6083A4F82CCC844D4C8C7D6AFC432@SJ1PR11MB6083.namprd11.prod.outlook.com>
Date: Mon, 21 Oct 2024 17:13:41 +0000
From: "Luck, Tony" <tony.luck@...el.com>
To: Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>, Borislav Petkov
	<bp@...en8.de>
CC: Thomas Gleixner <tglx@...utronix.de>, Ingo Molnar <mingo@...hat.com>, Dave
 Hansen <dave.hansen@...ux.intel.com>, "x86@...nel.org" <x86@...nel.org>,
	"daniel.sneddon@...ux.intel.com" <daniel.sneddon@...ux.intel.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-pm@...r.kernel.org" <linux-pm@...r.kernel.org>,
	"linux-perf-users@...r.kernel.org" <linux-perf-users@...r.kernel.org>, Josh
 Poimboeuf <jpoimboe@...nel.org>, Srinivas Pandruvada
	<srinivas.pandruvada@...ux.intel.com>, "Rafael J. Wysocki"
	<rafael@...nel.org>, Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>,
	"Liang, Kan" <kan.liang@...ux.intel.com>, "andrew.cooper3@...rix.com"
	<andrew.cooper3@...rix.com>, Brice Goglin <brice.goglin@...il.com>, "Mario
 Limonciello" <mario.limonciello@....com>, Perry Yuan <Perry.Yuan@....com>,
	Dapeng Mi <dapeng1.mi@...ux.intel.com>
Subject: RE: [PATCH v4 02/10] x86/cpu/topology: Add CPU type to struct
 cpuinfo_topology

>> The core is born this way and then it changes... so this is its native
>> model ID? Weird...
>
> In a hybrid system the model number reported by CPUID could represent
> multiple core-types. As model number is same for all cores, it is
> insufficient to uniquely identify the microarchitecture of a core. I
> believe "native model ID" bridges that gap as it is specific to a core.

Example from <asm/intel-family.h>

#define INTEL_ALDERLAKE_L               IFM(6, 0x9A) /* Golden Cove / Gracemont */

#define INTEL_RAPTORLAKE                IFM(6, 0xB7) /* Raptor Cove / Enhanced Gracemont */

The native model number could be helpful to tell what each of your P-cores and E-cores
are based on. Could be useful when the same base core is used in more than one SoC
generation.

-Tony