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Message-ID: <2ac4604c-a765-48b1-84b2-8979f18c29a7@quicinc.com>
Date: Wed, 30 Oct 2024 12:23:57 +0530
From: Raviteja Laggyshetty <quic_rlaggysh@...cinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
CC: Georgi Djakov <djakov@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio
<konradybcio@...nel.org>,
Sibi Sankar <quic_sibis@...cinc.com>, <linux-arm-msm@...r.kernel.org>,
<linux-pm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
Odelu Kukatla
<quic_okukatla@...cinc.com>,
Mike Tipton <quic_mdtipton@...cinc.com>
Subject: Re: [PATCH V2 1/3] dt-bindings: interconnect: Add EPSS L3 compatible
for SA8775P
On 10/26/2024 8:15 PM, Dmitry Baryshkov wrote:
> On Sat, Oct 26, 2024 at 12:30:56PM +0000, Raviteja Laggyshetty wrote:
>> Add Epoch Subsystem (EPSS) L3 interconnect provider binding on
>> SA8775P SoCs.
>>
>> Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@...cinc.com>
>> ---
>> .../devicetree/bindings/interconnect/qcom,osm-l3.yaml | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
>> index 21dae0b92819..042ca44c32ec 100644
>> --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
>> +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
>> @@ -34,6 +34,10 @@ properties:
>> - qcom,sm8250-epss-l3
>> - qcom,sm8350-epss-l3
>> - const: qcom,epss-l3
>> + - items:
>> + - enum:
>> + - qcom,sa8775p-epss-l3
>> + - const: qcom,epss-l3-perf
>
> Why is it -perf? What's so different about it?
The EPSS instance in SA8775P uses PERF_STATE register instead of REG_L3_VOTE to scale L3 clocks.
So adding new generic compatible "qcom,epss-l3-perf" for PERF_STATE register based l3 scaling.
>
>>
>> reg:
>> maxItems: 1
>> --
>> 2.39.2
>>
>
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