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Message-ID: <ZypvePo2M0ZvC4RF@google.com>
Date: Tue, 5 Nov 2024 11:18:16 -0800
From: Sean Christopherson <seanjc@...gle.com>
To: Borislav Petkov <bp@...en8.de>
Cc: Borislav Petkov <bp@...nel.org>, X86 ML <x86@...nel.org>, Josh Poimboeuf <jpoimboe@...hat.com>,
Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>, kvm@...r.kernel.org,
LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] x86/bugs: Adjust SRSO mitigation to new features
On Tue, Nov 05, 2024, Borislav Petkov wrote:
> On Tue, Nov 05, 2024 at 10:10:20AM -0800, Sean Christopherson wrote:
> > All of the actual maintainers.
>
> Which maintainers do you mean? tip ones? If so, they're all shorted to
> x86@...nel.org.
>
> > AFAIK, Paolo doesn't subscribe to kvm@.
>
> Oh boy, srsly?! I thought I'd reach the proper crowd with
> kvm@...r.kernel.org...
It gets there, usually (as evidenced by my response). But even for me, there's
a non-zero chance I'll miss something that's only Cc'd to kvm@, largely because
kvm@ is used by all things virt, i.e. it's a bit noisy:
$ git grep kvm@ MAINTAINERS | wc -l
29
> > What does the bit actually do? I can't find any useful documentation, and the
> > changelog is equally useless.
>
> "Processors which set SRSO_MSR_FIX=1 support an MSR bit which mitigates SRSO
> across guest/host boundaries. Software may enable this by setting bit
> 4 (BpSpecReduce) of MSR C001_102E. This bit can be set once during boot and
> should be set identically across all processors in the system."
>
> From: https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf
>
> I think that's the only public info we have on that bit.
Heh, I found that. Not very helpful.
If you can't document the specifics, can you at least describe the performance
implications? It's practically impossible to give meaningful feedback without
having any idea what the magic bit does.
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