lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <2989559.o0KrE1Onz3@diego>
Date: Tue, 19 Nov 2024 14:51:58 +0100
From: Heiko Stübner <heiko@...ech.de>
To: srinivas.kandagatla@...aro.org, Diederik de Haas <didi.debian@...ow.org>
Cc: robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
 detlev.casanova@...labora.com, devicetree@...r.kernel.org,
 linux-arm-kernel@...ts.infradead.org, linux-rockchip@...ts.infradead.org,
 linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org,
 sebastian.reichel@...labora.com
Subject: Re: [PATCH 1/5] clk: rockchip: rk3576: define clk_otp_phy_g

Am Dienstag, 19. November 2024, 14:45:53 CET schrieb Diederik de Haas:
> On Tue Nov 19, 2024 at 2:29 PM CET, Heiko Stuebner wrote:
> > The phy clock of the OTP block is also present, but was not defined
> > so far. Though its clk-id already existed, so just define its location.
> >
> > Signed-off-by: Heiko Stuebner <heiko@...ech.de>
> > ---
> >  drivers/clk/rockchip/clk-rk3576.c | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/clk/rockchip/clk-rk3576.c b/drivers/clk/rockchip/clk-rk3576.c
> > index 595e010341f7..029939a98416 100644
> > --- a/drivers/clk/rockchip/clk-rk3576.c
> > +++ b/drivers/clk/rockchip/clk-rk3576.c
> > @@ -541,6 +541,8 @@ static struct rockchip_clk_branch rk3576_clk_branches[] __initdata = {
> >  			RK3576_CLKGATE_CON(5), 14, GFLAGS),
> >  	GATE(CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m", 0,
> >  			RK3576_CLKGATE_CON(5), 15, GFLAGS),
> > +	GATE(CLK_OTP_PHY_G, "clk_otp_phy_g", "xin24m", 0,
> > +			RK3588_CLKGATE_CON(6), 0, GFLAGS),
> 
> RK3588? 

darn copy-paste, thanks for noticing ;-)

At least the register and bit number is correct though ... according to the TRM.
So I messed up only the constant and did not notice due to the gate being
ungated by default of course.


Heiko



Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ