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Message-ID: <20241120063305.8135-3-friday.yang@mediatek.com>
Date: Wed, 20 Nov 2024 14:32:56 +0800
From: Friday Yang <friday.yang@...iatek.com>
To: Philipp Zabel <p.zabel@...gutronix.de>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>, AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>, Friday Yang
<friday.yang@...iatek.com>
CC: <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <linux-mediatek@...ts.infradead.org>,
<Project_Global_Chrome_Upstream_Group@...iatek.com>
Subject: [PATCH v2 2/2] reset: mediatek: Add reset controller driver for SMI
From: "Friday Yang" <friday.yang@...iatek.com>
In order to avoid the bus glitch issue, add a reset-controller
driver for performing reset management of SMI LARBs on MediaTek
platform.
Signed-off-by: Friday Yang <friday.yang@...iatek.com>
---
drivers/reset/Kconfig | 9 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-mediatek-smi.c | 156 +++++++++++++++++++++++++++++
3 files changed, 166 insertions(+)
create mode 100644 drivers/reset/reset-mediatek-smi.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 5b3abb6db248..07e606e530fc 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -153,6 +153,15 @@ config RESET_MCHP_SPARX5
help
This driver supports switch core reset for the Microchip Sparx5 SoC.
+config RESET_MTK_SMI
+ bool "MediaTek SMI Reset Driver"
+ depends on MTK_SMI || COMPILE_TEST
+ help
+ This option enables the reset controller driver for MediaTek SMI.
+ This reset driver is responsible for managing the reset signals
+ for SMI larbs. Say Y if you want to control reset signals for
+ MediaTek SMI larbs. Otherwise, say N.
+
config RESET_NPCM
bool "NPCM BMC Reset Driver" if COMPILE_TEST
default ARCH_NPCM
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 677c4d1e2632..1f5ba5696872 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_RESET_K210) += reset-k210.o
obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o
+obj-$(CONFIG_RESET_MTK_SMI) += reset-mediatek-smi.o
obj-$(CONFIG_RESET_NPCM) += reset-npcm.o
obj-$(CONFIG_RESET_NUVOTON_MA35D1) += reset-ma35d1.o
obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
diff --git a/drivers/reset/reset-mediatek-smi.c b/drivers/reset/reset-mediatek-smi.c
new file mode 100644
index 000000000000..0a2ffd9db670
--- /dev/null
+++ b/drivers/reset/reset-mediatek-smi.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Reset driver for MediaTek SMI module
+ *
+ * Copyright (C) 2024 MediaTek Inc.
+ */
+
+#include <linux/io.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+
+#include <dt-bindings/reset/mt8188-resets.h>
+
+#define to_mtk_smi_reset_data(_rcdev) \
+ container_of(_rcdev, struct mtk_smi_reset_data, rcdev)
+
+struct mtk_smi_larb_reset {
+ unsigned int offset;
+ unsigned int value;
+};
+
+static const struct mtk_smi_larb_reset rst_signal_mt8188[] = {
+ [MT8188_SMI_RST_LARB10] = { 0xC, BIT(0) },
+ [MT8188_SMI_RST_LARB11A] = { 0xC, BIT(0) },
+ [MT8188_SMI_RST_LARB11C] = { 0xC, BIT(0) },
+ [MT8188_SMI_RST_LARB12] = { 0xC, BIT(8) },
+ [MT8188_SMI_RST_LARB11B] = { 0xC, BIT(0) },
+ [MT8188_SMI_RST_LARB15] = { 0xC, BIT(0) },
+ [MT8188_SMI_RST_LARB16B] = { 0xA0, BIT(4) },
+ [MT8188_SMI_RST_LARB17B] = { 0xA0, BIT(4) },
+ [MT8188_SMI_RST_LARB16A] = { 0xA0, BIT(4) },
+ [MT8188_SMI_RST_LARB17A] = { 0xA0, BIT(4) },
+};
+
+struct mtk_smi_larb_plat {
+ const struct mtk_smi_larb_reset *reset_signal;
+ const unsigned int larb_reset_nr;
+};
+
+struct mtk_smi_reset_data {
+ const struct mtk_smi_larb_plat *larb_plat;
+ struct reset_controller_dev rcdev;
+ void __iomem *base;
+};
+
+static const struct mtk_smi_larb_plat mtk_smi_larb_mt8188 = {
+ .reset_signal = rst_signal_mt8188,
+ .larb_reset_nr = ARRAY_SIZE(rst_signal_mt8188),
+};
+
+static int mtk_smi_larb_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
+{
+ struct mtk_smi_reset_data *data = to_mtk_smi_reset_data(rcdev);
+ const struct mtk_smi_larb_plat *larb_plat = data->larb_plat;
+ const struct mtk_smi_larb_reset *larb_rst = larb_plat->reset_signal + id;
+ unsigned int val, offset = larb_rst->offset;
+ void __iomem *base = data->base;
+
+ val = readl(base + offset);
+ val |= larb_rst->value;
+ writel(val, base + offset);
+
+ return 0;
+}
+
+static int mtk_smi_larb_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
+{
+ struct mtk_smi_reset_data *data = to_mtk_smi_reset_data(rcdev);
+ const struct mtk_smi_larb_plat *larb_plat = data->larb_plat;
+ const struct mtk_smi_larb_reset *larb_rst = larb_plat->reset_signal + id;
+ unsigned int val, offset = larb_rst->offset;
+ void __iomem *base = data->base;
+
+ val = readl(base + offset);
+ val &= ~larb_rst->value;
+ writel(val, base + offset);
+
+ return 0;
+}
+
+static int mtk_smi_larb_reset(struct reset_controller_dev *rcdev, unsigned long id)
+{
+ mtk_smi_larb_reset_assert(rcdev, id);
+
+ return mtk_smi_larb_reset_deassert(rcdev, id);
+}
+
+static const struct reset_control_ops mtk_smi_reset_ops = {
+ .reset = mtk_smi_larb_reset,
+ .assert = mtk_smi_larb_reset_assert,
+ .deassert = mtk_smi_larb_reset_deassert,
+};
+
+static int mtk_smi_reset_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ const struct mtk_smi_larb_plat *larb_plat = of_device_get_match_data(dev);
+ struct device_node *np = dev->of_node, *reset_node;
+ struct mtk_smi_reset_data *data;
+ struct resource res;
+ void __iomem *base;
+
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ reset_node = of_parse_phandle(np, "mediatek,larb-rst", 0);
+ if (!reset_node)
+ return -EINVAL;
+
+ if (of_address_to_resource(reset_node, 0, &res)) {
+ of_node_put(reset_node);
+ return -EINVAL;
+ }
+
+ base = devm_ioremap_resource(dev, &res);
+ if (IS_ERR(base)) {
+ of_node_put(reset_node);
+ return PTR_ERR(base);
+ }
+
+ of_node_put(reset_node);
+ data->larb_plat = larb_plat;
+ data->base = base;
+ data->rcdev.owner = THIS_MODULE;
+ data->rcdev.ops = &mtk_smi_reset_ops;
+ data->rcdev.of_node = np;
+ data->rcdev.nr_resets = larb_plat->larb_reset_nr;
+ data->rcdev.dev = dev;
+ platform_set_drvdata(pdev, data);
+
+ return devm_reset_controller_register(dev, &data->rcdev);
+}
+
+static const struct of_device_id mtk_smi_larb_reset_of_match[] = {
+ { .compatible = "mediatek,mt8188-smi-reset", .data = &mtk_smi_larb_mt8188 },
+ { },
+};
+MODULE_DEVICE_TABLE(of, mtk_smi_larb_reset_of_match);
+
+static struct platform_driver mtk_smi_reset_driver = {
+ .probe = mtk_smi_reset_probe,
+ .driver = {
+ .name = "mediatek-smi-reset",
+ .of_match_table = mtk_smi_larb_reset_of_match,
+ },
+};
+module_platform_driver(mtk_smi_reset_driver);
+
+MODULE_AUTHOR("Friday.Yang@...iatek.com");
+MODULE_DESCRIPTION("MediaTek SMI Reset Driver");
+MODULE_LICENSE("GPL");
--
2.46.0
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