linux-kernel - Re: [PATCH v7 09/12] x86/process: Clear hardware feedback history for AMD processors

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Message-ID: <355c1c37-ef04-4209-8e05-66d6d295a98a@intel.com>
Date: Mon, 2 Dec 2024 08:38:59 -0800
From: Dave Hansen <dave.hansen@...el.com>
To: Mario Limonciello <mario.limonciello@....com>,
 Borislav Petkov <bp@...en8.de>
Cc: Thomas Gleixner <tglx@...utronix.de>, Ingo Molnar <mingo@...hat.com>,
 Dave Hansen <dave.hansen@...ux.intel.com>,
 "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" <x86@...nel.org>,
 "H . Peter Anvin" <hpa@...or.com>, "Rafael J . Wysocki" <rafael@...nel.org>,
 "Gautham R . Shenoy" <gautham.shenoy@....com>,
 Perry Yuan <perry.yuan@....com>, Brijesh Singh <brijesh.singh@....com>,
 Peter Zijlstra <peterz@...radead.org>, Li RongQing <lirongqing@...du.com>,
 "open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)"
 <linux-kernel@...r.kernel.org>, "open list:ACPI"
 <linux-acpi@...r.kernel.org>,
 "open list:AMD PSTATE DRIVER" <linux-pm@...r.kernel.org>,
 Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>
Subject: Re: [PATCH v7 09/12] x86/process: Clear hardware feedback history for
 AMD processors

On 11/30/24 06:07, Mario Limonciello wrote:
> --- a/arch/x86/kernel/process_64.c
> +++ b/arch/x86/kernel/process_64.c
> @@ -709,6 +709,10 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
>  	/* Load the Intel cache allocation PQR MSR. */
>  	resctrl_sched_in(next_p);
>  
> +	/* Reset hw history on AMD CPUs */
> +	if (cpu_feature_enabled(X86_FEATURE_AMD_WORKLOAD_CLASS))
> +		wrmsrl(AMD_WORKLOAD_HRST, 0x1);
> +
>  	return prev_p;

Could we do a little refactoring here, please?  This, plus the
resctrl_sched_in() is sure starting to look like a pattern.  It would be
nice to have a single, common function that 32-bit and 64-bit call at
the end of __switch_to().

The X86_BUG_SYSRET_SS_ATTRS hunk can probably go in there too.