linux-kernel - Re: [PATCH v3 1/5] dt-bindings: pci: Add Sophgo SG2042 PCIe host

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID:
 <PN0PR01MB5662DF3C3D71A274A2E5B9C2FEC72@PN0PR01MB5662.INDPRD01.PROD.OUTLOOK.COM>
Date: Fri, 21 Feb 2025 11:29:20 +0800
From: Chen Wang <unicorn_wang@...look.com>
To: Bjorn Helgaas <helgaas@...nel.org>
Cc: Chen Wang <unicornxw@...il.com>, kw@...ux.com,
 u.kleine-koenig@...libre.com, aou@...s.berkeley.edu, arnd@...db.de,
 bhelgaas@...gle.com, conor+dt@...nel.org, guoren@...nel.org,
 inochiama@...look.com, krzk+dt@...nel.org, lee@...nel.org,
 lpieralisi@...nel.org, manivannan.sadhasivam@...aro.org, palmer@...belt.com,
 paul.walmsley@...ive.com, pbrobinson@...il.com, robh@...nel.org,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
 linux-pci@...r.kernel.org, linux-riscv@...ts.infradead.org,
 chao.wei@...hgo.com, xiaoguang.xing@...hgo.com, fengchun.li@...hgo.com
Subject: Re: [PATCH v3 1/5] dt-bindings: pci: Add Sophgo SG2042 PCIe host


On 2025/2/20 2:22, Bjorn Helgaas wrote:
> On Wed, Feb 12, 2025 at 01:54:11PM +0800, Chen Wang wrote:
>> On 2025/2/12 12:25, Bjorn Helgaas wrote:
>> [......]
>>>> pcie_rc1 and pcie_rc2 share registers in cdns_pcie1_ctrl. By using
>>>> different "sophgo,core-id" values, they can distinguish and access
>>>> the registers they need in cdns_pcie1_ctrl.
>>> Where does cdns_pcie1_ctrl fit in this example?  Does that enclose
>>> both pcie_rc1 and pcie_rc2?
>> cdns_pcie1_ctrl is defined as a syscon node,  which contains registers
>> shared by pcie_rc1 and pcie_rc2. In the binding yaml file, I drew a diagram
>> to describe the relationship between them, copy here for your quick
>> reference:
>>
>> +                     +-- Core (Link0) <---> pcie_rc1  +-----------------+
>> +                     |                                |                 |
>> +      Cadence IP 2 --+                                | cdns_pcie1_ctrl |
>> +                     |                                |                 |
>> +                     +-- Core (Link1) <---> pcie_rc2  +-----------------+
>>
>> The following is an example with cdns_pcie1_ctrl added. For simplicity, I
>> deleted pcie_rc0.
> Looks good.  It would be nice if there were some naming similarity or
> comment or other hint to connect sophgo,core-id with the syscon node.
>
>> pcie_rc1: pcie@...2000000 {
>>      compatible = "sophgo,sg2042-pcie-host";
>>      ...... // host bride level properties
>>      linux,pci-domain = <1>;
>>      sophgo,core-id = <0>;
>>      sophgo,syscon-pcie-ctrl = <&cdns_pcie1_ctrl>;
>>      port {
>>          // port level properties
>>          vendor-id = <0x1f1c>;
>>          device-id = <0x2042>;
>>          num-lanes = <2>;
>>      };
>> };
>>
>> pcie_rc2: pcie@...2800000 {
>>      compatible = "sophgo,sg2042-pcie-host";
>>      ...... // host bride level properties
>>      linux,pci-domain = <2>;
>>      sophgo,core-id = <1>;
>>      sophgo,syscon-pcie-ctrl = <&cdns_pcie1_ctrl>;
>>      port {
>>          // port level properties
>>          vendor-id = <0x1f1c>;
>>          device-id = <0x2042>;
>>          num-lanes = <2>;
>>      }
>>
>> };
>>
>> cdns_pcie1_ctrl: syscon@...3800000 {
>>      compatible = "sophgo,sg2042-pcie-ctrl", "syscon";
>>      reg = <0x70 0x63800000 0x0 0x800000>;
>> };

Hi, Bjorn ,

I find dtb check will report error due to "port" is not a evaulated 
property for pcie host. Should we add a vendror specific property for this?

Or do you have any example for reference?

Thanks,

Chen