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Message-ID: <0dffeb3b-63b3-266e-d1e9-b8adda7cc0ec@oss.qualcomm.com>
Date: Thu, 27 Feb 2025 09:41:41 +0530
From: Krishna Chaitanya Chundru <krishna.chundru@....qualcomm.com>
To: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
Cc: Bjorn Helgaas <bhelgaas@...gle.com>,
        Lorenzo Pieralisi <lpieralisi@...nel.org>,
        Krzysztof WilczyƄski <kw@...ux.com>,
        Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        chaitanya chundru <quic_krichai@...cinc.com>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>,
        cros-qcom-dts-watchers@...omium.org, Jingoo Han <jingoohan1@...il.com>,
        Bartosz Golaszewski <brgl@...ev.pl>, quic_vbadigan@...cnic.com,
        amitk@...nel.org, dmitry.baryshkov@...aro.org,
        linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
        jorge.ramirez@....qualcomm.com,
        Bartosz Golaszewski <bartosz.golaszewski@...aro.org>
Subject: Re: [PATCH v4 00/10] PCI: Enable Power and configure the TC956x PCIe
 switch



On 2/27/2025 9:29 AM, Manivannan Sadhasivam wrote:
> On Thu, Feb 27, 2025 at 09:27:47AM +0530, Manivannan Sadhasivam wrote:
>> On Tue, Feb 25, 2025 at 03:03:57PM +0530, Krishna Chaitanya Chundru wrote:
>>> TC956x is the PCIe switch which has one upstream and three downstream
>>> ports. To one of the downstream ports ethernet MAC is connected as endpoint
>>> device. Other two downstream ports are supposed to connect to external
>>> device. One Host can connect to TC956x by upstream port.
>>>
>>> TC956x switch power is controlled by the GPIO's. After powering on
>>> the switch will immediately participate in the link training. if the
>>> host is also ready by that time PCIe link will established.
>>>
>>> The TC956x needs to configured certain parameters like de-emphasis,
>>> disable unused port etc before link is established.
>>>
>>> As the controller starts link training before the probe of pwrctl driver,
>>> the PCIe link may come up as soon as we power on the switch. Due to this
>>> configuring the switch itself through i2c will not have any effect as
>>> this configuration needs to done before link training. To avoid this
>>> introduce two functions in pci_ops to start_link() & stop_link() which
>>> will disable the link training if the PCIe link is not up yet.
>>>
>>> Enable global IRQ for PCIe controller so that recan can happen when
>>> link was up through global IRQ.
>>>   
>>
>> Move these patches to a separate series.
>>
> 
> Or you can just drop them. I have a series that adds global IRQ to most of the
> SoCs and sc7280 is one of them.
> 
> - Mani
fine for me, I will drop.

- Krishna Chaitanya.
> 

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