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Message-ID: <20250402113201.151195-6-j-choudhary@ti.com>
Date: Wed, 2 Apr 2025 17:02:01 +0530
From: Jayesh Choudhary <j-choudhary@...com>
To: <robh@...nel.org>, <krzk+dt@...nel.org>, <conor+dt@...nel.org>,
<nm@...com>, <vigneshr@...com>, <afd@...com>, <s-vadapalli@...com>,
<linux-kernel@...r.kernel.org>
CC: <kristo@...nel.org>, <rogerq@...nel.org>, <kishon@...nel.org>,
<devicetree@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
<j-choudhary@...com>
Subject: [PATCH v2 5/5] arm64: dts: ti: k3-am64: Add PCIe ctrl node to main_conf region
From: Andrew Davis <afd@...com>
This region is used for controlling the function of the PCIe IP. It is
compatible with "ti,j784s4-pcie-ctrl", add this here and use it with
the PCIe node.
Signed-off-by: Andrew Davis <afd@...com>
[j-choudhary@...com: Add changes to k3-am642-evm-pcie0-ep.dtso]
Signed-off-by: Jayesh Choudhary <j-choudhary@...com>
---
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 7 ++++++-
arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso | 2 +-
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index 324eb44c258d..d872a624601c 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -51,6 +51,11 @@ chipid@14 {
reg = <0x00000014 0x4>;
};
+ pcie0_ctrl: pcie-ctrl@...0 {
+ compatible = "ti,j784s4-pcie-ctrl", "syscon";
+ reg = <0x4070 0x4>;
+ };
+
serdes_ln_ctrl: mux-controller@...0 {
compatible = "reg-mux";
reg = <0x4080 0x4>;
@@ -1036,7 +1041,7 @@ pcie0_rc: pcie@...2000 {
interrupt-names = "link_state";
interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
- ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
+ ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
max-link-speed = <2>;
num-lanes = <1>;
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso b/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso
index 6b029539e0db..432751774853 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso
@@ -46,6 +46,6 @@ pcie0_ep: pcie-ep@...2000 {
max-functions = /bits/ 8 <1>;
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
- ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
+ ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
};
};
--
2.34.1
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