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Message-ID: <8f60f4a6-6356-427e-9c4c-145081f8e14f@amd.com>
Date: Thu, 3 Apr 2025 17:14:49 +0530
From: Neeraj Upadhyay <Neeraj.Upadhyay@....com>
To: Thomas Gleixner <tglx@...utronix.de>, linux-kernel@...r.kernel.org
Cc: bp@...en8.de, mingo@...hat.com, dave.hansen@...ux.intel.com,
Thomas.Lendacky@....com, nikunj@....com, Santosh.Shukla@....com,
Vasant.Hegde@....com, Suravee.Suthikulpanit@....com, David.Kaplan@....com,
x86@...nel.org, hpa@...or.com, peterz@...radead.org, seanjc@...gle.com,
pbonzini@...hat.com, kvm@...r.kernel.org, kirill.shutemov@...ux.intel.com,
huibo.wang@....com, naveen.rao@....com, francescolavra.fl@...il.com
Subject: Re: [PATCH v3 02/17] x86/apic: Initialize Secure AVIC APIC backing
page
On 4/3/2025 5:07 PM, Thomas Gleixner wrote:
> On Tue, Apr 01 2025 at 17:06, Neeraj Upadhyay wrote:
>> +enum es_result savic_register_gpa(u64 gpa)
>> +{
>> + struct ghcb_state state;
>> + struct es_em_ctxt ctxt;
>> + unsigned long flags;
>> + enum es_result res;
>> + struct ghcb *ghcb;
>> +
>> + local_irq_save(flags);
>
> guard(irqsave)();
>
Ok
>> + ghcb = __sev_get_ghcb(&state);
>> +
>> + vc_ghcb_invalidate(ghcb);
>> +
>> + /* Register GPA for the local CPU */
>> + ghcb_set_rax(ghcb, -1ULL);
>> + ghcb_set_rbx(ghcb, gpa);
>> + res = sev_es_ghcb_hv_call(ghcb, &ctxt, SVM_VMGEXIT_SECURE_AVIC,
>> + SVM_VMGEXIT_SECURE_AVIC_REGISTER_GPA, 0);
>
> https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#line-breaks
>
Ok, will align with "ghcb" arg on previous line.
- Neeraj
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