linux-kernel - Re: [PATCH v4 2/5] dt-bindings: pci: cadence: Extend compatible for new EP configurations

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Message-ID: <20250425-drained-flyover-4275720a1f5a@spud>
Date: Fri, 25 Apr 2025 15:48:31 +0100
From: Conor Dooley <conor@...nel.org>
To: Manikandan Karunakaran Pillai <mpillai@...ence.com>
Cc: "hans.zhang@...tech.com" <hans.zhang@...tech.com>,
	"bhelgaas@...gle.com" <bhelgaas@...gle.com>,
	"lpieralisi@...nel.org" <lpieralisi@...nel.org>,
	"kw@...ux.com" <kw@...ux.com>,
	"manivannan.sadhasivam@...aro.org" <manivannan.sadhasivam@...aro.org>,
	"robh@...nel.org" <robh@...nel.org>,
	"krzk+dt@...nel.org" <krzk+dt@...nel.org>,
	"conor+dt@...nel.org" <conor+dt@...nel.org>,
	"peter.chen@...tech.com" <peter.chen@...tech.com>,
	"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v4 2/5] dt-bindings: pci: cadence: Extend compatible for
 new EP configurations

On Fri, Apr 25, 2025 at 02:19:11AM +0000, Manikandan Karunakaran Pillai wrote:
> >
> >
> >On Thu, Apr 24, 2025 at 04:29:35PM +0100, Conor Dooley wrote:
> >> On Thu, Apr 24, 2025 at 09:04:41AM +0800, hans.zhang@...tech.com wrote:
> >> > From: Manikandan K Pillai <mpillai@...ence.com>
> >> >
> >> > Document the compatible property for HPA (High Performance
> >Architecture)
> >> > PCIe controller EP configuration.
> >>
> >> Please explain what makes the new architecture sufficiently different
> >> from the existing one such that a fallback compatible does not work.
> >>
> >> Same applies to the other binding patch.
> >
> >Additionally, since this IP is likely in use on your sky1 SoC, why is a
> >soc-specific compatible for your integration not needed?
> >
> 
> The sky1 SoC support patches will be developed and submitted by the Sky1
> team separately.

Why? Cixtech sent this patchset, they should send it with their user.

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