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Message-Id: <20250428115049.2064955-1-pritam.sutar@samsung.com>
Date: Mon, 28 Apr 2025 17:20:49 +0530
From: Pritam Manohar Sutar <pritam.sutar@...sung.com>
To: krzk@...nel.org, s.nawrocki@...sung.com, cw00.choi@...sung.com,
alim.akhtar@...sung.com, mturquette@...libre.com, sboyd@...nel.org,
sunyeal.hong@...sung.com
Cc: linux-samsung-soc@...r.kernel.org, linux-clk@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
rosa.pila@...sung.com, dev.tailor@...sung.com, faraz.ata@...sung.com, Pritam
Manohar Sutar <pritam.sutar@...sung.com>, stable <stable@...nel.org>
Subject: [PATCH] clk: samsung: correct clock summary for hsi1 block
When debugfs is mounted to check clk_summary, 'mout_hsi1_usbdrd_user'
shows 400Mhz instead of 40Mhz. Snippet of the clock summary is given
as below
dout_shared2_div4 1 1 0 400000000 0 0 50000 Y ...
mout_hsi1_usbdrd_user 0 0 0 400000000 0 0 50000 Y ...
dout_clkcmu_hsi1_usbdrd 0 0 0 40000000 0 0 50000 Y ...
Hence corrected the clk-tree for the cmu_hsi1 & the corrected clock
summary is as mentioned below.
dout_shared2_div4 1 1 0 400000000 0 0 50000 Y ...
mout_clkcmu_hsi1_usbdrd 0 0 0 400000000 0 0 50000 Y ...
dout_clkcmu_hsi1_usbdrd 0 0 0 40000000 0 0 50000 Y ...
mout_hsi1_usbdrd_user 0 0 0 40000000 0 0 50000 Y ...
Fixes: 485e13fe2fb6 ("clk: samsung: add top clock support for ExynosAuto v920 SoC")
Cc: stable <stable@...nel.org>
Signed-off-by: Pritam Manohar Sutar <pritam.sutar@...sung.com>
---
drivers/clk/samsung/clk-exynosautov920.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynosautov920.c b/drivers/clk/samsung/clk-exynosautov920.c
index dc8d4240f6de..b0561faecfeb 100644
--- a/drivers/clk/samsung/clk-exynosautov920.c
+++ b/drivers/clk/samsung/clk-exynosautov920.c
@@ -1393,7 +1393,7 @@ static const unsigned long hsi1_clk_regs[] __initconst = {
/* List of parent clocks for Muxes in CMU_HSI1 */
PNAME(mout_hsi1_mmc_card_user_p) = {"oscclk", "dout_clkcmu_hsi1_mmc_card"};
PNAME(mout_hsi1_noc_user_p) = { "oscclk", "dout_clkcmu_hsi1_noc" };
-PNAME(mout_hsi1_usbdrd_user_p) = { "oscclk", "mout_clkcmu_hsi1_usbdrd" };
+PNAME(mout_hsi1_usbdrd_user_p) = { "oscclk", "dout_clkcmu_hsi1_usbdrd" };
PNAME(mout_hsi1_usbdrd_p) = { "dout_tcxo_div2", "mout_hsi1_usbdrd_user" };
static const struct samsung_mux_clock hsi1_mux_clks[] __initconst = {
--
2.34.1
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