linux-kernel - RE: [PATCH v8 11/16] cxl/pci: Unifi CXL trace logging for CXL Endpoints and CXL Ports

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <c21ab32695484da996df84988dddbd0d@huawei.com>
Date: Wed, 7 May 2025 16:28:19 +0000
From: Shiju Jose <shiju.jose@...wei.com>
To: Jonathan Cameron <jonathan.cameron@...wei.com>, Terry Bowman
	<terry.bowman@....com>
CC: "linux-cxl@...r.kernel.org" <linux-cxl@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
	"nifan.cxl@...il.com" <nifan.cxl@...il.com>, "dave@...olabs.net"
	<dave@...olabs.net>, "dave.jiang@...el.com" <dave.jiang@...el.com>,
	"alison.schofield@...el.com" <alison.schofield@...el.com>,
	"vishal.l.verma@...el.com" <vishal.l.verma@...el.com>,
	"dan.j.williams@...el.com" <dan.j.williams@...el.com>, "bhelgaas@...gle.com"
	<bhelgaas@...gle.com>, "mahesh@...ux.ibm.com" <mahesh@...ux.ibm.com>,
	"ira.weiny@...el.com" <ira.weiny@...el.com>, "oohall@...il.com"
	<oohall@...il.com>, "Benjamin.Cheatham@....com" <Benjamin.Cheatham@....com>,
	"rrichter@....com" <rrichter@....com>, "nathan.fontenot@....com"
	<nathan.fontenot@....com>, "Smita.KoralahalliChannabasappa@....com"
	<Smita.KoralahalliChannabasappa@....com>, "lukas@...ner.de"
	<lukas@...ner.de>, "ming.li@...omail.com" <ming.li@...omail.com>,
	"PradeepVineshReddy.Kodamati@....com" <PradeepVineshReddy.Kodamati@....com>
Subject: RE: [PATCH v8 11/16] cxl/pci: Unifi CXL trace logging for CXL
 Endpoints and CXL Ports

>-----Original Message-----
>From: Jonathan Cameron <jonathan.cameron@...wei.com>
>Sent: 23 April 2025 17:45
>To: Terry Bowman <terry.bowman@....com>
>Cc: linux-cxl@...r.kernel.org; linux-kernel@...r.kernel.org; linux-
>pci@...r.kernel.org; nifan.cxl@...il.com; dave@...olabs.net;
>dave.jiang@...el.com; alison.schofield@...el.com; vishal.l.verma@...el.com;
>dan.j.williams@...el.com; bhelgaas@...gle.com; mahesh@...ux.ibm.com;
>ira.weiny@...el.com; oohall@...il.com; Benjamin.Cheatham@....com;
>rrichter@....com; nathan.fontenot@....com;
>Smita.KoralahalliChannabasappa@....com; lukas@...ner.de;
>ming.li@...omail.com; PradeepVineshReddy.Kodamati@....com; Shiju Jose
><shiju.jose@...wei.com>
>Subject: Re: [PATCH v8 11/16] cxl/pci: Unifi CXL trace logging for CXL Endpoints
>and CXL Ports
>
>On Wed, 26 Mar 2025 20:47:12 -0500
>Terry Bowman <terry.bowman@....com> wrote:
>
>Unify.
>
>
>> CXL currently has separate trace routines for CXL Port errors and CXL
>> Endpoint errors. This is inconvnenient for the user because they must
>> enable 2 sets of trace routines. Make updates to the trace logging
>> such that a single trace routine logs both CXL Endpoint and CXL Port
>> protocol errors.
>>
>> Also, CXL RAS errors are currently logged using the associated CXL
>> port's name returned from devname(). They are typically named with
>> 'port1', 'port2', etc. to indicate the hierarchial location in the CXL topology.
>> But, this doesn't clearly indicate the CXL card or slot reporting the
>> error.
>>
>> Update the logging to also log the corresponding PCIe devname. This
>> will give a PCIe SBDF or ACPI object name (in case of CXL HB). This
>> will provide details helping users understand which physical slot and
>> card has the error.
>>
>> Below is example output after making these changes.
>>
>> Correctable error example output:
>> cxl_port_aer_correctable_error: device=port1 (0000:0c:00.0) parent=root0
>(pci0000:0c) status='Received Error From Physical Layer'
>>
>> Uncorrectable error example output:
>> cxl_port_aer_uncorrectable_error: device=port1 (0000:0c:00.0) parent=root0
>(pci0000:0c) status: 'Memory Byte Enable Parity Error' first_error: 'Memory
>Byte Enable Parity Error'
>
>I'm not sure the pcie parent is adding much... Why bother with that?
>
>Shiju, is this going to affect rasdaemon handling?

Hi Jonathan,

Yes. Renaming the existing fields in the trace events will result failure
while parsing the fields in the rasdaemon.

>
>I'd assume we can't just rename fields in the tracepoints and combining them
>will also presumably make a mess?
>
>Jonathan
>
[...]
>>

Thanks,
Shiju