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Message-ID: <003143c8-6dd2-4484-a641-7418f686c388@amd.com>
Date: Wed, 7 May 2025 13:28:32 -0500
From: "Bowman, Terry" <terry.bowman@....com>
To: Gregory Price <gourry@...rry.net>
Cc: linux-cxl@...r.kernel.org, linux-kernel@...r.kernel.org,
 linux-pci@...r.kernel.org, nifan.cxl@...il.com, dave@...olabs.net,
 jonathan.cameron@...wei.com, dave.jiang@...el.com,
 alison.schofield@...el.com, vishal.l.verma@...el.com,
 dan.j.williams@...el.com, bhelgaas@...gle.com, mahesh@...ux.ibm.com,
 ira.weiny@...el.com, oohall@...il.com, Benjamin.Cheatham@....com,
 rrichter@....com, nathan.fontenot@....com,
 Smita.KoralahalliChannabasappa@....com, lukas@...ner.de,
 ming.li@...omail.com, PradeepVineshReddy.Kodamati@....com
Subject: Re: [PATCH v8 00/16] Enable CXL PCIe port protocol error handling and
 logging



On 5/6/2025 6:06 PM, Gregory Price wrote:
> On Wed, Mar 26, 2025 at 08:47:01PM -0500, Terry Bowman wrote:
>> This patchset updates CXL Protocol Error handling for CXL Ports and CXL
>> Endpoints (EP). The reach of this patchset grew from CXL Ports to include
>> EPs as well because updating the handling for all devices is preferable
>> over supporting multiple handling paths.
>>
>> This patchset is a continuation of v7 and can be found here:
>> https://lore.kernel.org/linux-cxl/20250211192444.2292833-1-terry.bowman@amd.com/
>>
> I've been testing this for stability on a fair number of boxes for some
> time - backported to v6.13. Haven't seen any major issues related to
> this set in that time. Outside my normal wheelhouse, but for the sake
> of runtime stability:
>
> Tested-by: Gregory Price <gourry@...rry.net>
>
> Trying to get more explicit testing feedback from RAS folks.
>
> (note: there appears to be some conflicting changes in v6.15-rc4+ that
> a bit outside my current timeline to forward port and test.)
>
> ~Gregory
Thanks Greg.

-Terry

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