linux-kernel - Re: [PATCH 0/5] Add support for the IPQ5018 Internal GE PHY

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Message-ID:
 <DS7PR19MB88839AC485C51FD2940BEE6D9D67A@DS7PR19MB8883.namprd19.prod.outlook.com>
Date: Wed, 28 May 2025 08:57:33 +0400
From: George Moussalem <george.moussalem@...look.com>
To: "Rob Herring (Arm)" <robh@...nel.org>
Cc: Florian Fainelli <f.fainelli@...il.com>,
 Russell King <linux@...linux.org.uk>, Heiner Kallweit
 <hkallweit1@...il.com>, devicetree@...r.kernel.org,
 Andrew Lunn <andrew@...n.ch>, Conor Dooley <conor+dt@...nel.org>,
 Jakub Kicinski <kuba@...nel.org>, Bjorn Andersson <andersson@...nel.org>,
 Philipp Zabel <p.zabel@...gutronix.de>, "David S. Miller"
 <davem@...emloft.net>, linux-clk@...r.kernel.org, netdev@...r.kernel.org,
 linux-kernel@...r.kernel.org, Konrad Dybcio <konradybcio@...nel.org>,
 Michael Turquette <mturquette@...libre.com>, Paolo Abeni
 <pabeni@...hat.com>, linux-arm-msm@...r.kernel.org,
 Eric Dumazet <edumazet@...gle.com>, Krzysztof Kozlowski
 <krzk+dt@...nel.org>, Stephen Boyd <sboyd@...nel.org>
Subject: Re: [PATCH 0/5] Add support for the IPQ5018 Internal GE PHY

Hi Rob,

On 5/27/25 21:56, Rob Herring (Arm) wrote:
> 
> On Sun, 25 May 2025 21:56:03 +0400, George Moussalem wrote:
>> The IPQ5018 SoC contains an internal Gigabit Ethernet PHY with its
>> output pins that provide an MDI interface to either an external switch
>> in a PHY to PHY link architecture or directly to an attached RJ45
>> connector.
>>
>> The PHY supports 10/100/1000 mbps link modes, CDT, auto-negotiation and
>> 802.3az EEE.
>>
>> The LDO controller found in the IPQ5018 SoC needs to be enabled to drive
>> power to the CMN Ethernet Block (CMN BLK) which the GE PHY depends on.
>> The LDO must be enabled in TCSR by writing to a specific register.
>>
>> In a phy to phy architecture, DAC values need to be set to accommodate
>> for the short cable length.
>>
>> Signed-off-by: George Moussalem <george.moussalem@...look.com>
>>
>> Signed-off-by: George Moussalem <george.moussalem@...look.com>
>> ---
>> George Moussalem (5):
>>        dt-bindings: net: qca,ar803x: Add IPQ5018 Internal GE PHY support
>>        clk: qcom: gcc-ipq5018: fix GE PHY reset
>>        net: phy: qcom: at803x: Add Qualcomm IPQ5018 Internal PHY support
>>        arm64: dts: qcom: ipq5018: add MDIO buses
>>        arm64: dts: qcom: ipq5018: Add GE PHY to internal mdio bus
>>
>>   .../devicetree/bindings/net/qca,ar803x.yaml        |  23 +++
>>   arch/arm64/boot/dts/qcom/ipq5018.dtsi              |  51 ++++-
>>   drivers/clk/qcom/gcc-ipq5018.c                     |   2 +-
>>   drivers/net/phy/qcom/Kconfig                       |   2 +-
>>   drivers/net/phy/qcom/at803x.c                      | 221 ++++++++++++++++++++-
>>   5 files changed, 287 insertions(+), 12 deletions(-)
>> ---
>> base-commit: ebfff09f63e3efb6b75b0328b3536d3ce0e26565
>> change-id: 20250430-ipq5018-ge-phy-db654afa4ced
>>
>> Best regards,
>> --
>> George Moussalem <george.moussalem@...look.com>
>>
>>
>>
> 
> 
> My bot found new DTB warnings on the .dts files added or changed in this
> series.
> 
> Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
> are fixed by another series. Ultimately, it is up to the platform
> maintainer whether these warnings are acceptable or not. No need to reply
> unless the platform maintainer has comments.
> 
> If you already ran DT checks and didn't see these error(s), then
> make sure dt-schema is up to date:
> 
>    pip3 install dtschema --upgrade
> 
> 
> This patch series was applied (using b4) to base:
>   Base: base-commit ebfff09f63e3efb6b75b0328b3536d3ce0e26565 not known, ignoring
>   Base: attempting to guess base-commit...
>   Base: remotes/arm-soc/qcom/dt64-11-g43fefd6c7129 (exact match)
> 
> If this is not the correct base, please add 'base-commit' tag
> (or use b4 which does this automatically)
> 
> New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/qcom/' for 20250525-ipq5018-ge-phy-v1-0-ddab8854e253@...look.com:
> 
> arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dtb: ethernet-phy@7: clocks: [[7, 36], [7, 37]] is too long
> 	from schema $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
> arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dtb: ethernet-phy@7: clocks: [[7, 36], [7, 37]] is too long
> 	from schema $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
> 

These pop up as the phy needs to enable 2 clocks (RX and TX) during 
probe which conflicts with the restriction set in ethernet-phy.yaml 
which says:

   clocks:
     maxItems: 1

Would you like me to add a condition in qca,ar803x.yaml on the 
compatible (PHY ID) to override it and set it to two?

Likewise on resets, right now we I've got 1 reset (a bitmask that 
actually triggers 4 resets) to conform to the bindings. If, as per 
ongoing discussion, I need to list all resets, it will also conflict 
with the restriction on resets of max 1 item.

> 
> 
> 
> 

Thanks,
Georg