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Message-ID: <aFLtJriFlGbbcjFm@lizhi-Precision-Tower-5810>
Date: Wed, 18 Jun 2025 12:45:26 -0400
From: Frank Li <Frank.li@....com>
To: Richard Zhu <hongxing.zhu@....com>
Cc: l.stach@...gutronix.de, lpieralisi@...nel.org, kwilczynski@...nel.org,
mani@...nel.org, robh@...nel.org, bhelgaas@...gle.com,
shawnguo@...nel.org, s.hauer@...gutronix.de, kernel@...gutronix.de,
festevam@...il.com, linux-pci@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, imx@...ts.linux.dev,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v1 2/2] PCI: imx6: Add external reference clock mode
support
On Wed, Jun 18, 2025 at 03:48:48PM +0800, Richard Zhu wrote:
> The PCI Express reference clock of i.MX9 PCIes might come from external
> clock source. Add the external reference clock mode support.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@....com>
> ---
> drivers/pci/controller/dwc/pci-imx6.c | 34 ++++++++++++++++++++-------
> 1 file changed, 26 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 5a38cfaf989b..04c720377546 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -149,6 +149,7 @@ struct imx_pcie {
> struct gpio_desc *reset_gpiod;
> struct clk_bulk_data *clks;
> int num_clks;
> + bool enable_ext_refclk;
> struct regmap *iomuxc_gpr;
> u16 msi_ctrl;
> u32 controller_id;
> @@ -259,13 +260,24 @@ static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
> IMX95_PCIE_PHY_CR_PARA_SEL,
> IMX95_PCIE_PHY_CR_PARA_SEL);
>
> - regmap_update_bits(imx_pcie->iomuxc_gpr,
> - IMX95_PCIE_PHY_GEN_CTRL,
> - IMX95_PCIE_REF_USE_PAD, 0);
> - regmap_update_bits(imx_pcie->iomuxc_gpr,
> - IMX95_PCIE_SS_RW_REG_0,
> - IMX95_PCIE_REF_CLKEN,
> - IMX95_PCIE_REF_CLKEN);
> + if (imx_pcie->enable_ext_refclk) {
> + /* External clock is used as reference clock */
> + regmap_update_bits(imx_pcie->iomuxc_gpr,
> + IMX95_PCIE_PHY_GEN_CTRL,
> + IMX95_PCIE_REF_USE_PAD,
> + IMX95_PCIE_REF_USE_PAD);
> + regmap_update_bits(imx_pcie->iomuxc_gpr,
> + IMX95_PCIE_SS_RW_REG_0,
> + IMX95_PCIE_REF_CLKEN, 0);
> + } else {
> + regmap_update_bits(imx_pcie->iomuxc_gpr,
> + IMX95_PCIE_PHY_GEN_CTRL,
> + IMX95_PCIE_REF_USE_PAD, 0);
> + regmap_update_bits(imx_pcie->iomuxc_gpr,
> + IMX95_PCIE_SS_RW_REG_0,
> + IMX95_PCIE_REF_CLKEN,
> + IMX95_PCIE_REF_CLKEN);
bool ext = imx_pcie->enable_ext_refclk;
regmap_update_bits(....
ext ? IMX95_PCIE_REF_USE_PAD: 0);
regmap_update_bits(...
ext ? 0: IMX95_PCIE_REF_CLKEN);
Frank
> + }
>
> return 0;
> }
> @@ -1600,7 +1612,7 @@ static int imx_pcie_probe(struct platform_device *pdev)
> struct imx_pcie *imx_pcie;
> struct device_node *np;
> struct device_node *node = dev->of_node;
> - int ret, domain;
> + int i, ret, domain;
> u16 val;
>
> imx_pcie = devm_kzalloc(dev, sizeof(*imx_pcie), GFP_KERNEL);
> @@ -1651,6 +1663,12 @@ static int imx_pcie_probe(struct platform_device *pdev)
> if (imx_pcie->num_clks < 0)
> return dev_err_probe(dev, imx_pcie->num_clks,
> "failed to get clocks\n");
> + for (i = 0; i < imx_pcie->num_clks; i++) {
> + if (strncmp(imx_pcie->clks[i].id, "ref", 3) == 0)
> + imx_pcie->enable_ext_refclk = false;
> + else
> + imx_pcie->enable_ext_refclk = true;
> + }
>
> if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_PHYDRV)) {
> imx_pcie->phy = devm_phy_get(dev, "pcie-phy");
> --
> 2.37.1
>
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