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Message-ID: <20250716014504.GAaHcEIIUgNOdu_n2s@fat_crate.local>
Date: Wed, 16 Jul 2025 03:45:04 +0200
From: Borislav Petkov <bp@...en8.de>
To: Andrew Cooper <andrew.cooper3@...rix.com>,
"H. Peter Anvin" <hpa@...or.com>
Cc: khaliidcaliy@...il.com, ardb@...nel.org, brgerst@...il.com,
dave.hansen@...ux.intel.com, hpa@...or.com,
linux-kernel@...r.kernel.org, mingo@...hat.com, tglx@...utronix.de,
ubizjak@...il.com, x86@...nel.org
Subject: Re: [PATCH v3] x86/boot: Avoid writing to cr4 twice in startup_64()
On Tue, Jul 15, 2025 at 10:21:20PM +0100, Andrew Cooper wrote:
> > diff
> > <https://lore.kernel.org/lkml/20250715181709.1040-1-khaliidcaliy@gmail.com/#iZ31arch:x86:kernel:head_64.S>
> > --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index
> > 4390a28f7dad..dfb5390e5c9a 100644 --- a/arch/x86/kernel/head_64.S +++
> > b/arch/x86/kernel/head_64.S @@ -222,12 +222,9 @@
> > SYM_INNER_LABEL(common_startup_64, SYM_L_LOCAL)
> > /* Even if ignored in long mode, set PSE uniformly on all logical CPUs. */
> > btsl $X86_CR4_PSE_BIT, %ecx
> > - movq %rcx, %cr4 - - /* - * Set CR4.PGE to re-enable global
> > translations. - */ + /* Set CR4.PGE to re-enable global translations. */ btsl $X86_CR4_PGE_BIT, %ecx
> > + movq %rcx, %cr4
>
> The comments are at best misleading, but you've broken the TLB flush
> being performed which depends on the double write.
>
> This logic is intentionally performing a write with CR4.PGE=0 followed
> by one with CR4.PGE=1 to flush all global mappings.
Thanks both of you for the catch - I didn't realize that fact. Zapped now.
So yeah, maybe there should be a comment explaining this subtlety.
Thx.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
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