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Message-ID: <19b62fb0-fb49-4a90-bff4-f5634547f2fe@kernel.org>
Date: Thu, 17 Jul 2025 16:39:23 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
Pankaj Patil <pankaj.patil@....qualcomm.com>, andersson@...nel.org,
linus.walleij@...aro.org, robh@...nel.org, krzk+dt@...nel.org,
conor+dt@...nel.org, quic_rjendra@...cinc.com
Cc: linux-arm-msm@...r.kernel.org, linux-gpio@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/2] pinctrl: qcom: Add glymur pinctrl driver
On 17/07/2025 13:52, Konrad Dybcio wrote:
>> +static const struct msm_pinctrl_soc_data glymur_tlmm = {
>> + .pins = glymur_pins,
>> + .npins = ARRAY_SIZE(glymur_pins),
>> + .functions = glymur_functions,
>> + .nfunctions = ARRAY_SIZE(glymur_functions),
>> + .groups = glymur_groups,
>> + .ngroups = ARRAY_SIZE(glymur_groups),
>> + .ngpios = 250,
>
> 251 (0..=250, incl. ufs reset)
The binding said 238 GPIOs...
>
> Konrad
Best regards,
Krzysztof
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