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Message-ID: <175493766084.138281.3748243184118825357.b4-ty@kernel.org>
Date: Mon, 11 Aug 2025 13:41:06 -0500
From: Bjorn Andersson <andersson@...nel.org>
To: mturquette@...libre.com,
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Varadarajan Narayanan <quic_varada@...cinc.com>
Subject: Re: (subset) [PATCH v7 0/4] Enable cpufreq for IPQ5424
On Mon, 11 Aug 2025 14:39:50 +0530, Varadarajan Narayanan wrote:
> CPU on Qualcomm ipq5424 is clocked by huayra PLL with RCG support.
> Add support for the APSS PLL, RCG and clock enable for ipq5424.
> The PLL, RCG register space are clubbed. Hence adding new APSS driver
> for both PLL and RCG/CBC control. Also the L3 cache has a separate pll
> modeled as ICC clock. The L3 pll needs to be scaled along with the CPU.
>
> v7: Fix 'Reviewed-by' placement for bindings patch
> Use enum instead of clock names for l3 pll
> Select IPQ_APSS_5424 if IPQ_GCC_5424 is enabled
>
> [...]
Applied, thanks!
[2/4] clk: qcom: apss-ipq5424: Add ipq5424 apss clock controller
commit: 5bf83c54bab5eb15a2749c6c52b6f96d425490bc
Best regards,
--
Bjorn Andersson <andersson@...nel.org>
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