linux-kernel - Re: [PATCH v7 2/4] clk: qcom: apss-ipq5424: Add ipq5424 apss clock controller

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Message-ID: <e410c5f5-227c-4852-9223-a935584fbb75@oss.qualcomm.com>
Date: Mon, 11 Aug 2025 12:32:56 +0200
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Varadarajan Narayanan <quic_varada@...cinc.com>, andersson@...nel.org,
        mturquette@...libre.com, sboyd@...nel.org, robh@...nel.org,
        krzk+dt@...nel.org, conor+dt@...nel.org, konradybcio@...nel.org,
        rafael@...nel.org, viresh.kumar@...aro.org, ilia.lin@...nel.org,
        djakov@...nel.org, linux-arm-msm@...r.kernel.org,
        linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-pm@...r.kernel.org
Cc: Sricharan Ramabadhran <quic_srichara@...cinc.com>,
        Md Sadre Alam <quic_mdalam@...cinc.com>
Subject: Re: [PATCH v7 2/4] clk: qcom: apss-ipq5424: Add ipq5424 apss clock
 controller

On 8/11/25 11:09 AM, Varadarajan Narayanan wrote:
> From: Sricharan Ramabadhran <quic_srichara@...cinc.com>
> 
> CPU on Qualcomm ipq5424 is clocked by huayra PLL with RCG support.
> Add support for the APSS PLL, RCG and clock enable for ipq5424.
> The PLL, RCG register space are clubbed. Hence adding new APSS driver
> for both PLL and RCG/CBC control. Also the L3 cache has a separate pll
> and needs to be scaled along with the CPU and is modeled as an ICC clock.
> 
> Co-developed-by: Md Sadre Alam <quic_mdalam@...cinc.com>
> Signed-off-by: Md Sadre Alam <quic_mdalam@...cinc.com>
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@...cinc.com>
> [ Removed clock notifier, moved L3 pll to icc-clk, used existing
> alpha pll structure ]
> Signed-off-by: Varadarajan Narayanan <quic_varada@...cinc.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>

Konrad