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Message-ID: <175495482431.157244.8781382660149123331.b4-ty@kernel.org>
Date: Mon, 11 Aug 2025 18:27:07 -0500
From: Bjorn Andersson <andersson@...nel.org>
To: lpieralisi@...nel.org,
	kwilczynski@...nel.org,
	mani@...nel.org,
	robh@...nel.org,
	bhelgaas@...gle.com,
	sfr@...b.auug.org.au,
	qiang.yu@....qualcomm.com,
	linux-pci@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	konradybcio@...nel.org,
	krzk+dt@...nel.org,
	conor+dt@...nel.org,
	linux-arm-msm@...r.kernel.org,
	devicetree@...r.kernel.org,
	Wenbin Yao <quic_wenbyao@...cinc.com>
Cc: krishna.chundru@....qualcomm.com,
	quic_vbadigan@...cinc.com,
	quic_mrana@...cinc.com,
	quic_cang@...cinc.com
Subject: Re: (subset) [PATCH v5 0/3] arm64: qcom: x1e80100-qcp: Add power supply and sideband signals for PCIe RC


On Tue, 22 Jul 2025 17:11:48 +0800, Wenbin Yao wrote:
> The first patch enables the PCI Power Control driver to control the power
> state of PCI slots. The second patch adds the bus topology of PCIe domain 3
> on x1e80100 platform. The third patch adds perst, wake and clkreq sideband
> signals, and describe the regulators powering the rails of the PCI slots in
> the devicetree for PCIe3 controller and PHY device.
> 
> The patchset has been modified based on comments and suggestions.
> 
> [...]

Applied, thanks!

[2/3] arm64: dts: qcom: x1e80100: add bus topology for PCIe domain 3
      commit: 6facfaff0fe3b4d5903bed6164eb5e60ee6cdb8f
[3/3] arm64: dts: qcom: x1e80100-qcp: enable pcie3 x8 slot for X1E80100-QCP
      commit: df758a868dbc90cae98044d52a9d753575f50cfa

Best regards,
-- 
Bjorn Andersson <andersson@...nel.org>

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